r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 606

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
25.2.6
Note:
Table 25.3
Note:
4 MHz
5 MHz
20 MHz
Bits TCS20 to TCS25 (Period 2 cycle count select bits)
b10
b12
b13
b14
b15
b11
1. When the TCS2C bit is set to 0 (the number of cycles for period 2 is selected by bits TCS20 to TCS25), bits
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
Count Source Frequency
1. Value after reset.
After Reset
After Reset
TCS20 to TCS25 are enabled.
These bits are used to set the number of cycles for period 2 (period when CHxA = L, CHxB = Hi-Z, and CHxC
= Hi-Z).
Address 06B0Ah
Symbol
Symbol
Symbol
TCS2C
TCS20
TCS21
TCS22
TCS23
TCS24
TCS25
TCS30
TCS31
TCS32
TCS33
TCS34
TCS35
TSCU Timing Control Register 1 (TSCUTCR1)
—
—
—
Bit
Bit
Preliminary document
Specifications in this document are tentative and subject to change.
Period 2 Cycle Example
TCS2C
b15
Period 2 cycle count select bits
(1)
Nothing is assigned. The write value must be 0. The read value is 0.
Period 2 control bit
Period 3 cycle count select bits
Nothing is assigned. The write value must be 0. The read value is 0.
b7
—
0
0
b14
b6
—
—
0
0
Bit Name
1 Cycle
250 ns
200 ns
50 ns
TCS25
TCS35
b13
b5
0
0
TCS24
TCS34
b12
b4
0
0
2 Cycles
500 ns
400 ns
100 ns
TCS23
TCS33
0: The number of cycles for period 2 is selected
1: The number of cycles for period 2 is 0 (skip)
b13b12b11b10 b9 b8
b11
b5 b4 b3 b2 b1 b0
0 0 0 0 0 0: 1 cycle
0 0 0 0 0 1: 2 cycles (after reset)
0 0 0 0 1 0: 3 cycles
1 1 1 1 1 1: 64 cycles
0 0 0 0 0 0: 1 cycle (after reset)
0 0 0 0 0 1: 2 cycles
0 0 0 0 1 0: 3 cycles
1 1 1 1 1 1: 64 cycles
b3
0
0
by bits TCS20 to TCS25
(1)
TCS22
TCS32
b10
b2
0
0
3 Cycles
Function
750 ns
600 ns
150 ns
TCS21
TCS31
b1
b9
0
0
TCS20
TCS30
25. Sensor Control Unit
b0
b8
1
0
64 Cycles
Page 575 of 725
12.8  s
3.2  s
16  s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—