r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 506

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.7
21.3.2.2
Figure 21.7 shows an Operation Example during Data Transmission (Clock Synchronous Communication
Mode, 8-Bit SSU Data Transfer Length). During data transmission, the synchronous serial communication unit
operates as described below. (The data transfer length can be set from 8 to 16 bits using the SSBR register.)
When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a
slave device, it outputs data synchronized with the input clock.
When the TE_NAKIE bit in the SIER register is set to 1 (transmission enabled) before writing the transmit data
to the SITDR register, the TDRE bit in the SISR register is automatically set to 0 (data is not transferred from
registers SITDR to SISDR) and the data is transferred from registers SITDR to SISDR. Then, the TDRE bit is
set to 1 (data is transferred from registers SITDR to SISDR) and transmission is started. If the TIE bit in the
SIER register is 1 at this time, a TXI interrupt request is generated.
When one frame of data is transferred while the TDRE bit is 0, data is transferred from registers SITDR to
SISDR and the next frame transmission is started. If the 8th bit is transmitted while the TDRE bit is 1, the
TEND bit in the SISR register is set to 1 (the TDRE bit is 1 when the last bit of transmit data is transmitted) and
the state is retained. If the TEIE bit in the SIER register is 1 (transmit end interrupt request enabled) at this time,
a TEI interrupt request is generated. The SSCK pin is held high after transmission is completed.
Transmission cannot be performed while the ORER_AL bit in the SISR register is 1 (overrun error). Confirm
that the ORER_AL bit is 0 before transmission.
Figure 21.8 shows a Sample Flowchart for Data Transmission (Clock Synchronous Communication Mode).
SISR register
SISR register
• MS = 0 (clock synchronous communication mode), CPHS = 0 (data change at odd edge),
TDRE bit in
TEND bit in
CPOS_WAIT = 0 (high when clock stops), MLS = 1 (LSB-first transfer), and BS3 to BS0 = 1000b
(8 bits)
processing
Program
SSCK
SSO
Preliminary document
Specifications in this document are tentative and subject to change.
Data Transmission
Operation Example during Data Transmission (Clock Synchronous Communication
Mode, 8-Bit SSU Data Transfer Length)
Write data to SITDR register
TXI interrupt
request generated
b0
1
b1
2
One frame
b6
7
TXI interrupt request
generated
b7
8
BS0 to BS3: Bits in SSBR register
CPHS, CPOS_WAIT, MLS: Bits in SIMR1 register
MS: Bit in SIMR2 register
b0
1
TEI interrupt request
21. Clock Synchronous Serial Interface
One frame
generated
b6
7
b7
Clock stops
8
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