r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 135

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
10.2
Table 10.1
10.2.1
Notes:
System Clock Control Register 0
System Clock Control Register 1
System Clock Control Register 3
System Clock Control Register 4
High-Speed On-Chip Oscillator Control Register 0
STBY VDC Power Control Register
Module Standby Control Register 0
Module Standby Control Register 1
Module Standby Control Register 2
Module Standby Control Register 3
Module Standby Control Register 4
Table 10.1 lists the Register Configuration for Power Control.
After Reset
1. The CM04 bit can be set to 1 by a program, but cannot be set to 0.
2. The CM05 bit is used to stop the XIN clock when setting to high-speed on-chip oscillator mode or low-speed on-
3. P4_6 and P4_7 can be used as I/O ports only when the CM05 bit is 1 (XIN clock stops) and the CM13 bit in the
4. When an external clock is input, only the clock oscillation buffer stops and the clock input is accepted.
5. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
6. When the MCU exits stop mode or wait mode, do not set the CM05 bit again if switching to the XIN clock.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00008h
chip oscillator mode. This bit cannot be used to detect whether the XIN clock has stopped. To stop the XIN clock,
make the following settings:
(1) Set the CM06 bit to 1 (divide-by-8 mode)
(2) Set the OCD0 bit in the OCD register to 00b (oscillation stop detection function disabled).
(3) Set bits CM42 to CM40 in the CM4 register to 001b (fLOCO clock).
CM1 register is 0 (P4_6 and P4_7).
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register.
Symbol
Registers
Bit
Symbol
CM02
CM03
CM04
CM05
CM06
CM07
System Clock Control Register 0 (CM0)
—
—
Preliminary document
Specifications in this document are tentative and subject to change.
Register Configuration for Power Control
CM07
b7
Register Name
0
Reserved
Peripheral function clock stop bit in
wait mode
XCIN clock stop bit
XCIN buffer external input set bit
XIN clock (XIN-XOUT) stop bit
CPU clock division ratio select bit 0
XIN buffer external input set bit
CM06
b6
0
Bit Name
CM05
b5
1
CM04
b4
0
(2, 3)
(6)
MSTCR0
MSTCR1
MSTCR2
MSTCR3
MSTCR4
(1)
Symbol
SVDC
FRA0
CM0
CM1
CM3
CM4
(5)
CM03
b3
1
Set to 0.
0: System clock does not stop in wait mode
1: System clock stops in wait mode
0: Oscillates
1: Stops
0: External clock input from XCIN
1: Xtal used
0: Oscillates
1: Stops
0: Bits CM16 and CM17 in CM1 register
1: Divide-by-8 mode
0: Xtal used
1: External clock input from XOUT
enabled
CM02
After Reset
00101000b
00100000b
00000001b
(4)
b2
0
00h
00h
00h
00h
00h
00h
00h
00h
Function
b1
—
0
Address
0023Ch
0000Bh
0000Ch
0002Ch
0023Ah
0023Bh
00008h
00009h
00012h
00238h
00239h
b0
—
0
10. Power Control
Page 104 of 725
Access Size
8
8
8
8
8
8
8
8
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W