r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 212

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
13.4
13.4.1
13.4.2
13.4.3
13.4.4
• Do not generate any DTC activation sources before entering wait mode or during wait mode.
• Do not generate any DTC activation sources before entering stop mode or during stop mode.
• The TSCU DTC activation source can be used for DTC transfers during wait mode.
• Modify bits DTCENi0 to DTCENi7 only while an interrupt request corresponding to the bit is not generated.
• When the interrupt source flag in the status register for the peripheral function is 1, do not modify the
• Do not access the DTCENi registers using DTC transfers.
• Do not set the status register bit for the peripheral function to 0 using a DTC transfer.
• When the DTC activation source is SSU/I
• When the DTC activation source is SSU/I
• The TSCU DTC activation source must be used only for DTC transfers with interrupts set to be disabled.
• When the DTC activation source is either SSU/I
corresponding activation source bit among bits DTCENi0 to DTCENi7.
The RDRF bit in the SISR register is set to 0 (no data in the SIRDR register) by reading the SIRDR register.
However, the RDRF bit is not set to 0 by reading the SIRDR register when the DTC data transfer setting is
either of the following:
transfer. The TDRE bit in the SISR register is set to 0 (data is not transferred from registers SITDR to SISDR)
by writing to the SITDR register.
interrupt request is generated for the CPU in either of the following cases:
- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit in the DTCCRj
-When the DTC performs a data transfer that causes the DTCCTj register value to change to 0 in normal
-When the DTC performs a data transfer that causes the DTCCRj register value to change to 0 while the
Notes on DTC
register is 1 (interrupt generation enabled) in repeat mode.
mode.
RPTINT bit in the DTCCRj register is 1 in repeat mode.
DTC activation source
DTCENi Registers (i = 0 to 3, 5, or 6)
Peripheral Modules
Interrupt Requests
Preliminary document
Specifications in this document are tentative and subject to change.
2
C receive data full, read the SIRDR register using a DTC transfer.
2
C transmit data empty, write to the SITDR register using a DTC
2
C transmit data empty or flash memory ready status, no
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13. DTC