r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 555

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 22.4
Hardware LIN Read the Synch Break detection flag
Timer RJ Set the timer to start counting
Timer RJ Read the count status flag
Timer RJ Set the timer to stop counting
Timer RJ Read the count status flag
UART0 Communication via UART
UART0 Communication via UART
TE bit in U0C1 register  1
U0TB register  0055h
U0TB register  ID field
TSTART bit in TRJCR register  1
TCSTF bit in TRJCR register
TSTART bit in TRJCR register  0
TCSTF bit in TRJCR register
Preliminary document
Specifications in this document are tentative and subject to change.
Header Field Transmission Flowchart Example (2)
SBDCT bit in LINST register
SBDCT = 1?
TCSTF = 1?
TCSTF = 0?
YES
YES
YES
A
NO
NO
NO
A Synch Break for timer RJ is generated.
After writing 1 to the TSTART bit, if the
TRJ register of timer RJ is not read or
the register settings are not changed,
reading 1 from the TCSTF bit can be
omitted.
Zero or one cycle of the timer RJ count
source is required after timer RJ starts
counting before the TCSTF bit is set to
1.
A timer RJ interrupt can be used to end
Synch Break generation.
One or two cycles of the CPU clock are
required after Synch Break generation
ends before the SBDCT bit is set to 1.
After a timer RJ Synch Break is
generated, stop the timer count.
After writing 0 to the TSTART bit, if the
TRJ register of timer RJ is not read or
the register settings are not changed,
reading 0 from the TCSTF bit can be
omitted.
Zero or one cycle of the timer RJ count
source is required after timer RJ starts
counting before the TCSTF bit is set to
0.
The Synch Field is transmitted.
The ID field is transmitted.
22. Hardware LIN
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