r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 413

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 19.3
19.3.1.1
• Transmit timing example (internal clock selected)
• Receive timing example (external clock selected)
The above diagram applies for the following settings:
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (transmit data is output at the falling
• U0IRS bit in U0C1 register = 0 (transmit buffer empty)
fEXT: Frequency of external clock
The above diagram applies for the following settings:
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (transmit data is output at the falling
edge and receive data is input at the rising edge of the transfer clock)
edge and receive data is input at the rising edge of the transfer clock)
Transfer clock
U0C1 register
U0C1 register
U0C0 register
U0C1 register
U0C1 register
U0C1 register
U0C1 register
U0IR register
U0IR register
TXEPT bit in
U0RIF bit in
U0TIF bit in
RE bit in
TE bit in
TE bit in
RI bit in
TI bit in
TI bit in
Preliminary document
Specifications in this document are tentative and subject to change.
Operation Examples
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
RXD
TXD
CLK
CLK
1/f1
register to U0RB register
Dummy data is set in U0TB register
D0 D1 D2 D3 D4 D5 D6
Data is set in U0TB register
3/f1
From UART0 receive
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
1/fi
From U0TB register to UART0 transmit register
From U0TB register to UART0 transmit register
1/fEXT
Set to 0 when the DTC or the interrupt control circuit acknowledges an interrupt
from UART0 or set to 0 by a program
TCLK
Set to 0 when the DTC or the interrupt control circuit acknowledges an interrupt
from UART0 or set to 0 by a program
TC
Receive data is acquired
3/f1
1/fi
D7
D0 D1 D2 D3 D4 D5 D6
TC = TCLK = 2 (n + 1)/fi
The following requirements must be met when an input
to the CLK0 pin is high before data reception:
• TE bit in U0C1 register  1 (transmission enabled)
• RE bit in U0C1 register  1 (reception enabled)
• Dummy data is written to U0TB register
fi: Frequency of U0BRG count source (f1, f8, f32, or fC1)
n: Value set in U0BRG register
U0RB register is read
D7
Stops because TE bit is 0
D0 D1 D2 D3 D4 D5 D6
19. Serial Interface (UART0)
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D7