r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 431

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
20.2.1
Notes:
20.2.2
b7 to b0 If the setting value is n, U2BRG divides the count source by n + 1.
After Reset
After Reset
1. In multiprocessor mode, set to 100b (UART mode transfer data length: 7 bits) or 101b (UART mode transfer data
2. When setting bits SMD2 to SMD0 to 000b, set the TE bit in the U2C1 register to 0 (transmission disabled) and
3. When using as master in SIO/I
4. Can only be selected in UART mode and multiprocessor communication mode. In other modes, set to 0 (one
5. Can only be selected in UART mode. In other modes, because the PRYE bit is set to 0 (no parity bit), the value
6. Can only be selected in UART mode. In other modes, set to 0 (no parity bit).
7. Can only be set in UART mode. In other modes, set to 0 (not inverted). If the IOPOL bit is set to 1 (inverted), the
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 000C1h
Address 000C0h
length: 8 bits).
the RE bit to 0 (reception disabled).
(external clock).
stop bit).
set to this bit is invalid.
If the PRYE bit is set to 1, the following operation occurs.
polarities of the transmit data and receive data are inverted.
(Start, stop, and parity bits are included in the inversion.)
Write to the U2BRG register when transmission and reception are stopped.
Write to this register using the MOV instruction.
Set bits CLK0 and CLK1 in the U2C0 register before writing to the U2BRG register.
Symbol
Symbol
During transmission: Parity bit is added after transmit data.
During reception: Parity bit causes error checking to be performed.
Symbol
CKDIR
IOPOL
Bit
SMD0
SMD1
SMD2
PRYE
Bit
STPS
PRY
UART2 Transmit/Receive Mode Register (U2MR)
UART2 Bit Rate Register (U2BRG)
IOPOL
Preliminary document
Specifications in this document are tentative and subject to change.
b7
b7
—
0
0
Serial I/O mode select bits
Internal/external clock select bit
Stop bit length select bit
Odd/even parity select bit
Parity enable bit
TXD and RXD I/O polarity switch bit
(7)
PRYE
b6
b6
—
0
0
Bit Name
2
(6)
C mode, set to 0 (internal clock). When using as slave in SIO/I
PRY
b5
b5
—
0
0
(4)
Function
(5)
(1, 2)
STPS
b4
b4
—
0
0
(3)
CKDIR
Other than the above: Do not set.
0: Internal clock
1: External clock
0: One stop bit
1: Two stop bits
0: Odd parity
1: Even parity
0: Parity disabled
1: Parity enabled
0: Not inverted
1: Inverted
b2 b1 b0
0 0 0: Serial interface disabled
0 0 1: Clock synchronous serial I/O mode
0 1 0: I
1 0 0: UART mode, transfer data 7 bits long
1 0 1: UART mode, transfer data 8 bits long
1 1 0: UART mode, transfer data 9 bits long
b3
b3
—
0
0
2
C mode
SMD2
b2
b2
—
0
0
Function
SMD1
b1
b1
—
0
0
20. Serial Interface (UART2)
00h to FFh
SMD0
Setting Range
b0
b0
—
0
0
2
C mode, set to 1
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W