r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 722

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
29.3
29.3.1
29.3.2
To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) before setting the
CM10 bit in the CM1 register to 1 (stop mode). The 4 bytes of instruction data following the instruction that
sets the STPM bit to 1 are prefetched from the instruction queue and then the program stops.
Insert at least four NOP instructions following the JMP.B instruction immediately after the instruction that sets
the CM10 bit to 1.
• Program example for executing stop mode
To enter wait mode by setting the CM30 bit in the CM3 register to 1, set the FMR01 bit to 0 (CPU rewrite mode
disabled) before setting the CM30 bit to 1.
To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode
disabled) before executing the WAIT instruction. The 4 bytes of instruction data following the WAIT
instruction are prefetched from the instruction queue and then the program stops. Insert at least four NOP
instructions after the instruction that sets the CM30 bit to 1 (MCU enters wait mode) or the WAIT instruction.
• Program example for executing the WAIT instruction
• Program example for executing the instruction that sets the CM30 bit to 1
To perform DTC transfers using DTC activation by the TSCU function during wait mode, the following settings
are required:
• Set the FMR11 bit in flash memory control register 1 = 1 (flash memory operation during wait mode enabled)
• Set the FMR27 bit in flash memory control register 2 = 1 (low-current-consumption read mode enabled)
• Set the SVC0 bit in the STBY VDC power register = 0 (transition to low-power-consumption mode disabled)
Notes on Power Control
Stop Mode
Wait Mode
Preliminary document
Specifications in this document are tentative and subject to change.
LABEL_001:
BCLR
BSET
FSET
BSET
JMP.B
NOP
NOP
NOP
NOP
BCLR
FSET
WAIT
NOP
NOP
NOP
NOP
BCLR
BSET
FCLR
BSET
NOP
NOP
NOP
NOP
BCLR
FSET
1, FMR0
0, PRCR
I
0, CM1
LABEL_001
1, FMR0
I
1, FMR0
0, PRCR
I
0, CM3
0, PRCR
I
; CPU rewrite mode disabled
; Protection disabled
; Interrupt enabled
; Stop mode
; CPU rewrite mode disabled
; Interrupt enabled
; Wait mode
; CPU rewrite mode disabled
; Writing to CM3 register enabled
; Interrupt enabled
; Wait mode
; Writing to CM3 register disabled
; Interrupt enabled
29. Usage Notes
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