r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 737

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
29.12 Notes on Clock Synchronous Serial Interface
29.12.1 Notes on Synchronous Serial Communication Unit
29.12.2 Notes on I
29.12.3 ICE Bit in SICR1 Register and SIRST Bit in SICR2 Register
29.12.3.1 Conditions when Values of Bits are Undefined
29.12.3.2 Countermeasures
To use the synchronous serial communication unit, set the IICSEL bit in the IICCR register to 0 (SSU function
selected).
To use the I
(1) Do not use the I
(2) Communication using “Hs-MODE” cannot be performed. The maximum transfer rate is [a maximum of
(3) The low period of the SCL signal is [a minimum of 1.3  s] in “FAST-MODE”. Since the high-level/low-
(4) There must be a delay of [a minimum of 300 ns] for the SDA pin to change at the rising edge of the SCL
(5) There is no compatibility with the CBUS.
(6) 10-bit addressing cannot used.
(7) When a start condition is detected while data is transmitted in slave transmit mode, any address following
(8) Do not set 1111XXXb and 0000XXXb as slave addresses.
(9) When starting communication by the master after a stop condition is detected, always clear the STOP bit in
While the I
SICR2 register, the values of the BBSY bit in the SICR2 register and the STOP bit in the SISR register may be
undefined.
• When this module occupies the I
• While this module transmits data or an acknowledge in slave mode of the I
• When a start condition (falling of SDA when SCL is high) is input, the BBSY bit is set to 1.
• When a stop condition (rising of SDA when SCL is high) is input, the BBSY bit is set to 0.
• In master transmit mode, while SCL and SDA are both high, when 1 is written to the BBSY bit, 0 is written to
• In master transmit mode or master receive mode, while SDA is low and this module is the only device that
• When 1 is written to the MS bit in the SAR register, the BBSY bit is set to 0.
the SCP bit, and a start condition (falling of SDA when SCL is high) is output, the BBSY bit is set to 1.
pulls SCL low, when 0 is written to the BBSY bit, 0 is written to the SCP bit in the SICR2 register, and a stop
condition (rising of SDA when SCL is high) is output, the BBSY bit is set to 1.
400 kHz] in “FAST-MODE”.
level width of the duty cycle for this module is 50%/50%, this value is not reached during operation at 400
kHz. Therefore, the maximum transfer rate is 2.6  s for the SCL period (maximum transfer frequency is
384.6 kHz).
signal. The SDA digital delay for this module must be at least 3 x f1 cycles, care must be taken when the
reference clock f1 is set to 11 MHz or above. Set bits SDADLY1 and SDADLY0 to 01b or more.
that condition cannot be received and the operation is stopped. Initialize the module according to the flow
for resetting the control block.
the SISR register to 0.
Preliminary document
Specifications in this document are tentative and subject to change.
2
2
C bus interface is operating, when 0 is written to the ICE bit or 1 is written to the SIRST bit in the
C bus interface, set the IICSEL bit in the IICCR register to 1 (I
2
2
C interface with settings that do not comply with the I
C bus Interface
2
C bus in master mode of the I
2
C bus interface.
2
2
2
C bus function selected).
C specification.
C bus interface.
29. Usage Notes
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