r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 385

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 18.8
18.3.4
Lower 11-bit counter
Higher 4-bit counter
18.3.4.1
TREADJ register
TREIFR register
This function corrects input frequency errors in the fC1 clock. The correction amount is set by bits ADJ0 to
ADJ5 in the TREADJ register. The correction direction is set by bits MINUS and PLUS in the TREADJ
register. Time errors can be corrected by setting bits PLUS and MINUS to 10b (addition correction) when the
fC1 clock is slower than 32,768 Hz, and by setting these bits to 01b (subtraction correction) when the fC1 clock
is faster than 32,768 Hz.
For correction by software, when 1 is written to the MINUS or PLUS bit once, correction is performed only for
that one time. Figure 18.8 shows an Operation Example of Addition Correction by Software. For subtraction
correction by software, if the TADJSF bit in the TREIFR register is set to 1 (being corrected) immediately
before the counter value and the setting value of bits ADJ0 to ADJ5 are compared and match, subtraction
correction is performed during the current 1/16 second (refer to Figure 18.9). If the TADJSF bit is set to 1
immediately after the counter value and the setting value of bits ADJ0 to ADJ5 are compared and match,
subtraction correction is performed during the next 1/16 second period (refer to Figure 18.10).
TADJSF bit in
PLUS bit in
Clock Error Correction Function
Preliminary document
Specifications in this document are tentative and subject to change.
Correction by Software
Operation Example of Addition Correction by Software
7FEh
The above diagram applies under the following conditions:
• AADJE bit in TRECR register = 0 (automatic correction function disabled (correction by software enabled))
• M: Value set in bits ADJ0 to ADJ5 in TREADJ register
A
7FFh 000h 001h
Write 1 to PLUS bit
count source
3 cycles of
First 1/16 second
A + 1
• • • •
Lower 11-bit counter
Addition correction ends
overflow
7FFh
M
During the second 1/16 second, the count of the
correction amount for the M in 000h to (M - 1) is
omitted and the frequency is increased
M + 1
Second 1/16 second
A + 2
• • • •
7FFh 000h 001h
Page 354 of 725
18. Timer RE2
A + 3