r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 172

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Table 11.6
11.4
000b
001b
010b
011b
100b
101b
110b
111b
11.4.1
11.4.2
11.4.3
Bits ILVL2 to
The following describes enabling and disabling maskable interrupts and setting the priority for acknowledgement.
This description does not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register to
enable or disable a maskable interrupt. Whether an interrupt is requested or not is indicated by the IR bit in the
corresponding interrupt control register.
ILVL0
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. After the interrupt request is
acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (no interrupt
requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RC interrupt, the timer RE2 interrupt, the synchronous serial
communication unit interrupt, and the flash memory interrupt are different. Refer to 11.8 Timer RC Interrupt,
Timer RE2 Interrupt, Synchronous Serial Communication Unit Interrupt, and Flash Memory Interrupt
(Interrupts with Multiple Interrupt Request Sources).
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 11.6 lists the Interrupt Priority Level Settings. Table 11.7 lists the Interrupt Priority Levels Enabled by
IPL.
The following are the conditions when an interrupt is acknowledged:
• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Interrupt Control
I Flag
IR Bit
Bits ILVL2 to ILVL0, IPL
Interrupt Priority Level Settings
Preliminary document
Specifications in this document are tentative and subject to change.
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt Priority Level
Priority
High
Low
—
Table 11.7
000b
001b
010b
011b
100b
101b
110b
111b
IPL
Interrupt Priority Levels Enabled by
IPL
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts are disabled
Enabled Interrupt Priority Level
Page 141 of 725
11. Interrupts