r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 730

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
29.8
29.8.1
29.8.2
29.8.3
29.8.4
The following notes apply when the CCLR bit in the TRCCR1 register is set to 1 (TRCCNT counter is cleared
by input capture/compare match A).
• When writing a value to the TRCCNT register by a program while the CTS bit in the TRCMR register is set to
• If the timing when the TRCCNT register is set to 0000h and is written coincide, the value is not written and
If the TRCCNT register is written and read, the value before this register is written may be read. In this case,
execute the JMP.B instruction between the write and read instructions.
• Program Example
To set bits CKS2 to CKS0 in the TRCCR1 register to 111b (fHOCO-F), set fHOCO-F to a clock frequency
higher than the CPU clock frequency.
If the TRCSR register is written and read, the value before this register is written may be read. In this case,
execute the JMP.B instruction between the write and read instructions.
• Program Example
When switching the count source, stop the count before switching. After switching the count source, wait for at
least two cycles of the CPU clock before writing to the registers (at addresses 00138h to 0014Dh and 00158h to
0016Dh) associated with timer RC.
• Changing procedure
(1) Set the CTS bit in the TRCMR register to 0 (count stops).
(2) Change bits CKS0 to CKS2 in the TRCCR1 register.
(3) Wait for at least two cycles of the CPU clock.
(4) Write to the registers (at addresses 00138h to 0014Dh and 00158h to 0016Dh) associated with timer RC.
Notes:
1 (count starts), ensure that the write timing does not coincide with when the TRCCNT register is set to 0000h.
the TRCCNT register is set to 0000h.
Notes on Timer RC
1. Do not set the FRA00 bit to 0 (high-speed on-chip oscillator off) while fHOCO or fHOCO-F is selected
2. Do not change the division ratio of the high-speed on-chip oscillator set by the FRA2 register while
TRCCNT Register
TRCCR1 Register
TRCSR Register
Count Source Switching
L1:
L1:
as the count source.
fHOCO-F is selected as the count source.
Preliminary document
Specifications in this document are tentative and subject to change.
MOV.W
JMP.B
MOV.W
MOV.B
JMP.B
MOV.B
#XXXXh, TRCCNT
L1
TRCCNT, DATA
#XXh, TRCSR
L1
TRCSR, DATA
; Write
; JMP.B instruction
; Read
; Write
; JMP.B instruction
; Read
29. Usage Notes
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