r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 416

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
19.3.2
Table 19.6
Note:
Transfer data format
Transfer clock
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
1. If an overrun error occurs, the receive data (b0 to b8) in the U0RB register is undefined. The U0RIF bit in the
In clock asynchronous serial I/O mode, transmission and reception are performed at an arbitrary bit rate and in
an arbitrary format.
Table 19.6 lists the Clock Asynchronous Serial I/O Mode Specifications and Table 19.7 lists the Registers and
Settings Used in Clock Asynchronous Serial I/O Mode.
U0IR register remains unchanged.
Item
Clock Asynchronous Serial I/O (UART) Mode
Preliminary document
Specifications in this document are tentative and subject to change.
Clock Asynchronous Serial I/O Mode Specifications
• Start bit: 1 bit
• Parity bit: Odd, even, or none selectable
• Stop bits: 1 or 2 bits selectable
• The CKDIR bit in the U0MR register is 0 (internal clock): fj/16 (n + 1)
• The CKDIR bit in the U0MR register is 1 (external clock): fEXT/16 (n + 1)
To start transmission, the following requirements must be met:
• The TE bit in the U0C1 register is set to 1 (transmission enabled).
• The TI bit in the U0C1 register is set to 0 (data present in the U0TB register).
• The RE bit in the U0C1 register is set to 1 (reception enabled).
• Start bit detection
For transmission, one of the following can be selected.
For reception
• Overrun error
• Framing error
• Parity error
• Error sum flag
• Character bits (transfer data): 7, 8 or 9 bits selectable
To start reception, the following requirements must be met:
fj = f1, f8, f32, or fC1
n = Value set in the U0BRG register (00h to FFh)
fEXT (input from the CLK pin)
n = Value set in the U0BRG register (00h to FFh)
- The U0IRS bit in the U0C1 register is set to 0 (transmit buffer empty):
- The U0IRS bit in the U0C1 register is set to 1 (transmission completed):
When data is transferred from the UART0 receive register to the U0RB register (at
completion of reception).
This error occurs if the next data reception starts before the U0RB register is read and
the bit prior to the last stop bit in the next data is received.
This error occurs when the set number of stop bits is not detected.
This error occurs when parity is enabled, and the number of 1’s in the parity and
character bits do not match the set number of 1’s.
This flag is set to 1 if an overrun, framing, or parity error occurs.
When data is transferred from the U0TB register to the UART0 transmit register (at
start of transmission).
When data transmission from the UART0 transmit register is completed.
(1)
Specification
19. Serial Interface (UART0)
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