r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 533

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.25
21.4.2.5.2
21.4.2.6
The following shows the operation and software flow when a stop condition is detected during I
transmit operation.
(1) Set to slave receive mode.
(2) Clear the TDRE bit by software.
Note:
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal. Figures 21.26 and 21.27 show the Operation Timing in Slave Receive Mode (I
Interface Mode).
The receive procedure and operation in slave receive mode are as follows:
(1) Set the ICE bit in the SICR1 register to 1 (transfer operation enabled). Then, set bits CPOS_WAIT and
(2) When the slave address matches at the first frame after detecting the start condition, the slave device
(3) Read the SIRDR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF
(4) Reading of the last byte is also performed by reading the SIRDR register.
SISR register
SISR register
1. When a start condition is detected during slave transmit operation, any address following that condition
TDRE bit in
TEND bit in
processing
MLS in the SIMR1 register and bits CKS0 to CKS3 in the SICR1 register (initial setting). Next, set bits
TRS and MST in the SICR1 register to 0 and wait until the slave address matches in slave receive mode.
outputs the level set by the CEIE_ACKBT bit in the SIER register to the SDA pin between the falling edge
of the 8th clock cycle and the falling edge of the 9th clock cycle. Since the RDRF bit in the SISR register
is set to 1 at the rising edge of the 9th clock cycle, perform a dummy read of the SIRDR register (the read
data is unnecessary because it indicates the slave address and R/W).
bit is 1, the SCL signal is held low until the SIRDR register is read. The setting change of the acknowledge
signal returned to the master device before reading the SIRDR register takes effect from the following
transfer frame.
Program
cannot be received. Reset the control block and input a start condition again.
SDA
SCL
Preliminary document
Specifications in this document are tentative and subject to change.
Data Setup Time during Slave Transmit Operation
Slave Receive Operation
Operation when Stop Condition is Detected during I
Transmit Operation
bit 9 (ACK)
SCL signal is held low by slave device
(1)
Data setup time using
Transmit data is written
CKS3 bit
21. Clock Synchronous Serial Interface
bit 1
2
C Slave
bit 2
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2
C slave
2
C bus