r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 654

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
RDYSTI Bit (Flash ready status interrupt request flag)
BSYAEI Bit (Flash access error interrupt request flag)
LBDATA Bit (LBDATA monitor flag)
FST4 Bit (Program error flag)
When the RDYSTIE bit in the FMR0 register is 1 (flash ready status interrupt enabled) and auto-programming
or auto-erasure completes, or erase-suspend mode is entered, the RDYSTI bit is set to 1 (flash ready status
interrupt requested).
During interrupt handling, set the RDYSTI bit to 0 (no flash ready status interrupt requested).
[Condition for setting to 0]
Set to 0 by an interrupt handling program.
[Condition for setting to 1]
When the flash memory status changes from busy to ready while the RDYSTIE bit in the FMR0 register is 1,
the RDYSTI bit is set to 1.
The status is changed from busy to ready in the following states:
• Completion of erasing/programming the flash memory
• Suspend acknowledgement
• Completion of forcible termination
• Completion of the lock bit program
• Completion of the read lock bit status
• Completion of the block blank check
• When the flash memory can be read after it has been stopped.
If an auto-programming or auto-erase block is accessed while the BSYAEIE bit in the FMR0 register is 1 (flash
access error interrupt enabled), the BSYAEI bit is set to 1 (flash access error interrupt requested). During
interrupt handling, set the BSYAEI bit to 0 (no flash access error interrupt requested).
If a command sequence error, erase error, or program error occurs while the CMDERIE bit in the FMR0 register
is 1 (erase/write error interrupt enabled), the BSYAEI bit is set to 1 (flash access error interrupt requested).
During interrupt handling, execute the clear status register command and set the BSYAEI bit to 0 (no flash
access error interrupt requested).
[Conditions for setting to 0]
(1) Set to 0 by an interrupt handling program.
(2) Execute the clear status register command.
[Conditions for setting to 1]
(1) Read or write to the area that is being erased/written when the BSYAEIE bit in the FMR0 register is 1 and
(2) If a command sequence error, erase error, blank check error, or program error occurs when the CMDERIE
This is a read-only bit indicating the lock bit status. To confirm the lock bit status, execute the read lock bit
status command and read the LBDATA bit after the FST7 bit is set to 1 (ready).
The condition for updating this bit is when the program, erase, read lock bit status commands are generated.
When the read lock bit status command is input, the FST7 bit is set to 0 (busy). At the time when the FST7 bit
is set to 1 (ready), the lock bit status is stored in the LBDATA bit. The data in the LBDATA bit is retained until
the next command is input.
This is a read-only bit indicating the auto-programming status. The bit is set to 1 if a program error occurs;
otherwise, it is set to 0. Refer to 26.5.8 Full Status Check for details.
while the flash memory is busy.
Or, read the data flash area while erasing/writing to the program ROM area. (Note that the read value is
undefined in both cases. Writing has no effect.)
bit in the FMR0 register is 1 (erase/write error interrupt enabled).
Preliminary document
Specifications in this document are tentative and subject to change.
26. Flash Memory
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