r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 111

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
8.3.3
Table 8.4
Notes:
Count source
Count operation
Period
Watchdog timer
initialization conditions
Count start conditions
Count stop condition
Operation at underflow Watchdog timer reset (refer to 6.3.5 Watchdog Timer Reset .)
Registers, bits
1. Only write to the WDTR register while the watchdog timer is counting.
2. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 at address 0FFFFh with a flash
3. The CSPRO bit is set to 1 even if 0 is written to the CSPROINI bit in the OFS register. The CSPROINI bit cannot
When count source protection mode is enabled, the count source for the watchdog timer is the low-speed on-
chip oscillator clock. If the CPU clock is stopped when a program runs out of control, a clock will still be
supplied to the watchdog timer.
Table 8.4 lists the Watchdog Timer Specifications when Count Source Protection Mode is Enabled.
programmer.
be changed by a program. To set this bit, write 0 to bit 7 at address 0FFFFh with a flash programmer.
Item
When Count Source Protection Mode is Enabled
Preliminary document
Specifications in this document are tentative and subject to change.
Watchdog Timer Specifications when Count Source Protection Mode is Enabled
Low-speed on-chip oscillator clock for the watchdog timer
Decrement
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Ex.: When the low-speed on-chip oscillator clock is 125 kHz and bits WDTUFS1 and
• Reset
• 00h and then FFh are written to the WDTR register
• Underflow
The operation of the watchdog timer after a reset is selected by the WDTON bit
OFS register (address 0FFFFh).
• When the WDTON bit is 1 (watchdog timer stops after reset)
• When the WDTON bit is 0 (watchdog timer automatically starts after reset)
None (Once count has started, it will not stop even in wait mode or stop mode.)
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode
enabled)
• The low-speed on-chip oscillator for the watchdog timer oscillates.
• The RIS bit in the RISR register is set to 1 (watchdog timer reset).
Low-speed on-chip oscillator clock for the watchdog timer
The watchdog timer and the prescaler stop after a reset, and only start counting when the
WDTS register is written.
The watchdog timer and the prescaler automatically start counting after a reset.
WDTUFS0 are 00b (03FFh), the period is approx. 8.2 ms.
(3)
Count value of the watchdog timer (m)
, the following are automatically set:
Specification
(1)
8. Watchdog Timer
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(2)
in the