r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 333

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 17.14
(output change when TOB = 0)
(output change when TOB = 1)
In PWM2 mode, the TRCTRG input is used to output a pulse with an arbitrary delay time and width from the
TRCIOB pin.
Set bits TCEG1 and TCEG0 in the TRCCR2 register to 10b (falling edge) to set the falling edge for the
TRCTRG input. Set the CSTP bit in the TRCCR2 register to 0 (increment continues) to continue incrementing
when compare match A with the TRCGRA register occurs. Set the BUFEB bit in the TRCMR register to 1
(TRCGRD register is used as a buffer register for TRCRGB register) to set the TRCGRD register as the buffer
register. Set the TOB bit in the TRCCR1 register to 0 (output value is low) or 1 (output value is high) to set the
initial level of the output level to 0 or 1. Next, set the CCLR bit in the TRCCR1 register to 1 (TRCCNT counter
is cleared by input capture/compare match A) to clear the TRCCNT register by compare match A.
Figure 17.14 shows an Operation Example in PWM2 Mode when TRCTRG Input is Enabled, and Figure 17.15
shows an Operation Example in PWM2 Mode when TRCTRG Input is Disabled. These examples apply when
the PWM2 bit in the TRCMR register is set to 0 (PWM2 mode) and a waveform is output from the TRCIOB
pin.
In PWM2 mode, when the TOB bit in the TRCCR1 register is 0 (output value is low), the TRCTRG input edge
is cancelled while a high level is output from the TRCIOB pin. Likewise, when the TOB bit is 1 (output value is
high), the TRCTRG input edge is cancelled while a low level is output from the TRCIOB pin. In addition,
transfer from registers TRCGRD to TRCGRB is performed when a compare match with the TRCGRA register
or TRCTRG input occurs. However, if the TRCTRG input is cancelled depending on the level of the TRCIOB
pin, transfer from registers TRCGRD to TRCGRB is not performed.
TRCIOA/TRCTRG
TRCGRC register
TRCGRD register
TRCGRA register
TRCGRB register
TRCGRB register
Preliminary document
Specifications in this document are tentative and subject to change.
Operation Example in PWM2 Mode when TRCTRG Input is Enabled
TRCCNT register value
TRCIOB
TRCIOB
FFFFh
0000h
TOB: Bit in TRCCR1 register
TRCTRG input under the following states is cancelled.
• TOB = 0 (output value is low), during high-level output
• TOB = 1 (output value is high), during low-level output
A
A
B
B
C
C
D
Page 302 of 725
D
17. Timer RC
Time