r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 482

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.1.3
Table 21.4
Communication modes
I/O pins
Transfer clocks
Receive error detection
Interrupt sources
Selectable functions
The I
Philips I
there are differences among them.
Table 21.4 lists the I
Figure 21.3 shows an External Circuit Connection Example for Pins SCL and SDA and Table 21.5 lists the I
bus Interface Pin Configuration.
2
I
C bus interface is the circuit that performs serial communication based on the data transfer format of the
2
Item
2
C bus Interface
C bus. This interface consists of a channel: I
Preliminary document
Specifications in this document are tentative and subject to change.
I
2
C bus Interface Specifications
2
C bus Interface Specifications, Figure 21.2 shows the I
• I
• Clock synchronous serial mode
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
• When the MST bit in the SICR1 register is 0 (slave mode)
• When the MST bit in the SICR1 register is 1 (master mode)
• Overrun error detection (clock synchronous serial mode)
• I
• Clock synchronous serial mode: 4 sources
• I
• Clock synchronous serial mode
• SDA digital delay
2
2
2
- Master or slave device can be selected.
- Continuous transmission and reception are supported (because the shift,
- Start/stop conditions are automatically generated in master mode.
- Automatic loading of the acknowledge bit during transmission.
- Bit synchronization and wait function are included. (In master mode, the state of
- Direct drive of pins SCL and SDA (N-channel open-drain output) is supported.
Continuous transmission and reception are supported (because the shift, transmit,
and receive registers are independent).
External clock (input from the SCL pin)
Internal clock selected by bits CKS0 to CKS3 in the SICR1 register and bits
IICTCTWI and IICTCHALF in the IICCR register (output from the SCL pin)
Indicates an overrun error has occurred during reception. When the last bit of the
next data is received while the RDRF bit in the SISR register is 1 (data present in
the SIRDR register), the ORER_AL bit in the SISR register is set to 1 (overrun
error).
Transmit data empty (including when slave address matches), transmit end,
receive data full (including when slave address matches), arbitration lost, NACK
detection, and stop condition detection
Transmit data empty, transmit end, receive data full, and overrun error
The output level of the acknowledge signal during reception can be selected.
MSB first or LSB first can be selected as the data transfer direction.
The digital delay value of the SDA pin can be selected by bits SDADLY0 and
SDADLY1 in the IICCR register.
C bus interface mode
C bus interface mode: 6 sources
C bus interface mode
transmit, and receive registers are independent).
the SCL signal is monitored per bit and the timing is synchronized automatically.
If the transfer is not ready yet, the SCL signal is held low and the interface stands
by.)
2
C_0. This chapter describes these channels as I
Description
21. Clock Synchronous Serial Interface
2
C bus Interface Block Diagram,
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2
C unless
2
C