r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 463

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.18
Figure 20.19
(2) SCL2 Pin Low Output Hold Function 2
Transmit SCL
UART2 requires at maximum 1.5 cycles of the transfer clock after transmit data is written to the transmit
buffer until the transfer clock (SCL) is transmitted. In addition, because the SCL synchronization function
of UART2 is enabled from the first bit of SCL transmission, if another device transmits a first bit in the
period from after the start condition is generated until the SCL synchronization function is enabled, the bit
may be shifted. Therefore, SCL2 pin low output hold function 2 of UART2 was created to disable clock
transmission from other devices after the start condition is transmitted. By using this function, a low level
is output to the SCL2 pin at the same time that data is written to the transmit buffer, and other devices can
be put into a wait state. This function is enabled by setting the SWC2 bit to 1, and disabled by setting it to
0. This function should only be used when the MCU is being used as a master. Figure 20.19 shows the
Timing of SCL2 Pin Low Output Hold Function 2.
When not using SCL2 pin output function (SWC2 = 0)
When using SCL2 pin output function (SWC2 = 1)
Transmit SCL
Transmit SCL
SCL of other
SCL of other
Preliminary document
Specifications in this document are tentative and subject to change.
Timing of SCL2 Pin Low Output Hold Function 1
Timing of SCL2 Pin Low Output Hold Function 2
SWC
SWC2
device
SWC2
device
SDA2
SDA2
Set the SWC bit to 1
0
Completion of writing transmit data
Completion of writing transmit data
Note:
1. Bit shifted.
1st bit
Maximum 1.5 cycles
2nd bit
Secure over 1.5 cycles
of SCL
1st bit
The SCL2 pin is held low here
(When the IICM bit is 1, a UART2
receive interrupt is generated)
2nd bit
1st bit
1st bit
SCL synchronization function enabled
8th bit
SCL synchronization function enabled
9th bit
(Address comparison
processing)
2nd bit
2nd bit
3rd bit
20. Serial Interface (UART2)
Setting the SWC bit to 0
releases the SCL2 pin
from low output
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