r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 182

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
11.7
Table 11.11
Notes:
Table 11.12
• Instruction with 2-byte operation code
• Instruction with 1-byte operation code
Instructions other than above
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the AIADRij register (i = 0 or 1, j = L or H). This interrupt is used as a break function for the debugger.
When the on-chip debugger is used, do not set an address match interrupt (registers AIENi, AIADRij, and fixed
vector table) in the user system.
Set the start address of any instruction in the AIADRij register. The AIENi0 bit in the AIENi register can be used to
enable or disable the interrupt. The address match interrupt is not affected by the I flag in the FLG register and IPL.
The PC value (refer to 11.4.7 Saving Registers), which is saved on the stack when an address match interrupt
request is acknowledged, will differ depending on the instruction at the address indicated by the AIADRij register.
(The appropriate return address is not saved on the stack.) Therefore, when returning from the address match
interrupt, use one of the following methods:
• Rewrite the contents of the stack and use the REIT instruction to return.
• Use an instruction such as POP to restore the stack to its previous state where the interrupt request was
Table 11.11 lists the PC Value Saved when Address Match Interrupt Request is Acknowledged. Table 11.12 lists the
Correspondence between Address Match Interrupt Sources and Associated Registers.
ADD.B:S
OR.B:S
STNZ
CMP.B:S
JMPS
MOV.B:S
Address Match Interrupt Source
acknowledged. Then use a jump instruction to return.
1. PC value saved: Refer to 11.4.7 Saving Registers .
2. Operation code: Refer to the R8C/3xT-A Series Software Manual (R01US0007EJ) .
Address match interrupt 0
Address match interrupt 1
Instruction at Address Indicated by AIADRij Register (i = 0 or 1, j = L or H)
Address Match Interrupt
Preliminary document
Specifications in this document are tentative and subject to change.
PC Value Saved when Address Match Interrupt Request is Acknowledged
#IMM8, dest
#IMM8, dest
#IMM8, dest
#IMM8, dest
#IMM8
#IMM, dest (however, dest = A0 or A1)
Correspondence between Address Match Interrupt Sources and Associated
Registers
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code
below each syntax. Operation code is shown in the bold frame in the diagrams.
SUB.B:S
MOV.B:S
STZX
PUSHM
JSRS
Address Match Interrupt Enable Bit
(2)
(2)
#IMM8, dest
#IMM8, dest
#IMM81, #IMM82,dest
src
#IMM8
AIEN00
AIEN10
AND.B:S
STZ
POPM
#IMM8,dest
#IMM8,dest
dest
Address Match Interrupt Register
Address indicated by
AIADRij register + 2
Address indicated by
AIADRij register + 1
AIADR0j
AIADR1j
PC Value Saved
Page 151 of 725
11. Interrupts
(1)