r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 367

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
18.2.11 Timer RE2 Control Register (TRECR) in Compare Match Timer Mode
Notes:
TRECR register
RTCRST bit in
TREOE Bit (Timer RE2 output enable bit)
CCLR Bit (Counter clear enable bit)
1. Set the RTCRST bit to 0 after setting it to 1. For the initialized values, refer to each register value after a reset by
After reset by
Bit
b0
b1
b2
b3
b4
b5
b6
b7
After Reset
the RTCRST bit.
Change this bit when the RUN bit is set to 0 (count stops).
Change this bit when the RUN bit is set to 0 (count stops).
When registers TRESEC and TREMIN are compared and match, the CCLR bit is used to select whether to
initialize the TRESEC register. This bit is enabled only when the CS3 bit in the TRECSR register is 0.
Address 00177h
Symbol
RTCRST Timer RE2 reset bit
Symbol
TREOE Timer RE2 output enable bit
AADJE
LFLAG
CCLR
HR24
RUN
PM
Bit
Preliminary document
Specifications in this document are tentative and subject to change.
RUN
Set to 0.
Set to 0.
Counter clear enable bit
Set to 0.
Timer RE2 operation start bit
b7
0
0
HR24
b6
0
0
Bit Name
(1)
PM
b5
0
0
RTCRST
b4
0
X
0: TMRE2O output disabled
1: TMRE2O output enabled
0: TRESEC register initialization by compare
1: TRESEC register initialization by compare
0: Normal operation
1: The registers are initialized and the counter
0: Count stops
1: Count starts
match is disabled
match is enabled
control circuit is initialized.
CCLR
b3
X
0
LFLAG
b2
1
1
Function
TREOE
b1
X
0
AADJE
b0
0
0
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18. Timer RE2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R