r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 323

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 17.2
Figure 17.3
17.3.1
The TRCCNT register performs free-running or period count operations. Immediately after a reset, the
TRCCNT register functions as a free-running counter. When the CTS bit in the TRCMR register is set to 1
(count starts), count operation is started. When the TRCCNT register overflows from FFFFh to 0000h, the OVF
bit in the TRCSR register is set to 1, and an interrupt request is generated if the OVIE bit in the TRCIER
register is 1 (interrupt request (FOVI) by OVF flag is enabled).
Figure 17.2 shows an Example of Free-Running Counter Operation.
When the TRCGRA register for period setting is set as an output compare register and the CCLR bit in the
TRCCR1 register is set to 1, a period count operation is performed. When the count value matches the
TRCGRA register, the TRCCNT register is set to 0000h and the IMFA bit in the TRCSR register is set to 1. If
the corresponding IMIEA bit in the TRCIER register is 1 (interrupt request (IMIA) by IMFA bit is enabled) at
this time, an interrupt request is generated. The TRCCNT register continues increment operation from 0000h.
Figure 17.3 shows an Example of Period Counter Operation.
TRCGRA register
TRCCNT register value
Timer Mode
TRCCNT register value
FFFFh
0000h
CTS
OVF
Preliminary document
Specifications in this document are tentative and subject to change.
Example of Free-Running Counter Operation
Example of Period Counter Operation
0000h
IMFA
CTS
CTS: Bit in TRCMR register
OVF: Bit in TRCSR register
CTS: Bit in TRCMR register
IMFA: Bit in TRCSR register
Set to 0 by a program
Set to 0 by a program
Time
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Time
17. Timer RC