r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 136

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
10.2.2
Notes:
After Reset
1. If the CM10 bit is 1 (stop mode), the on-chip feedback register is disabled. If the CM10 bit is 1 (stop mode), when
2. When the SVC0 bit in the SVDC register is 1 (transition to low-power-consumption mode enabled), do not set the
3. Once the CM13 bit is set to 1 by a program, it cannot be set to 0. Set the CM13 bit to 1 to use P4_6 and P4_7 as
4. The CM14 bit can be set to 1 (low-speed on-chip oscillator off) when bits CM42 to CM40 in the CM4 register are
5. To use a voltage monitor 1 interrupt or a voltage monitor 2 interrupt (when the digital filter is used), set the CM14
6. When the CM06 bit in the CM0 register is 0 (bits CM16 and CM17 enabled), bits CM16 and CM17 are enabled.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00009h
the CM13 bit is 1 (XIN-XOUT pin), the XOUT (P4_7) pin is set to high. When the CM13 bit is 1, P4_6 and P4_7
are set to input state.
CM10 bit to 1 (stop mode).
the XCIN-XCOUT pin (the XCSEL bit in the PINSR register is 0 and the CM01 bit in the CM0 register is 1) or to
use as the XIN-XOUT pin.
000b (XIN clock). When bits CM42 to CM40 re set to 001b (fLOCO clock), the CM14 bit is set to 0 (low-speed on-
chip oscillator on). Writing 1 to this bit has no effect.
bit to 0 (low-speed on-chip oscillator on).
Symbol
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM1 register.
Bit
Symbol
CM10
CM11
CM12
CM13
CM14
CM16
CM17
System Clock Control Register 1 (CM1)
—
Preliminary document
Specifications in this document are tentative and subject to change.
CM17
b7
0
All clock stop control bit
XIN-XOUT on-chip feedback resistor
select bit
XCIN-XCOUT on-chip feedback
resistor select bit
Port/XIN-XOUT switch bit
Low-speed on-chip oscillator oscillation
stop bit
Reserved
CPU clock division select bits 1
CM16
b6
(4, 5)
0
Bit Name
b5
—
1
(1, 2)
(3)
CM14
b4
0
(6)
CM13
b3
0
0: Clocks oscillate
1: All clocks stop (stop mode)
0: On-chip feedback resistor enabled
1: On-chip feedback resistor disabled
0: I/O ports P4_6 and P4_7
1: XIN-XOUT pin
0: Low-speed on-chip oscillator on
1: Low-speed on-chip oscillator off
Set to 1.
b7 b6
0 0: Divide-by-1 mode
0 1: Divide-by-2 mode
1 0: Divide-by-4 mode
1 1: Divide-by-16 mode
CM12
b2
0
CM11
Function
b1
0
CM10
b0
0
10. Power Control
Page 105 of 725
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W