r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 275

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
16.3.1
Notes:
TCSTF Bit (Timer RB2 count status flag)
After Reset
1. For notes on using bits TSTART and TCSTF, refer to 16.8 Notes on Timer RB2 .
2. When the TSTART bit is set to 1 (count starts) and then the count is started, the TCSTF bit is set to 1 (count in
3. When 0 (count stops) is written to the TSTART bit and then the count is stopped, the TCSTF bit is set to 0 (count
4. When 1 (count is forcibly stopped) is written to the TSTOP bit, the counter, registers TRBPRE, TRBPR, and
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00130h (TRBCR_0)
progress). Do not access the registers associated with timer RB2 other than the TCSTF bit until this bit is set to
1.
stops). Do not access the registers associated with timer RB2 other than the TCSTF bit until this bit is set to 0.
TRBSC, bits TSTART and TCSTF, and bits TOSST, TOSSP, and TOSSTF in the TRBOCR register are initialized.
The TRBO output is also initialized.
[Conditions for setting to 0]
• When 0 is written to the TSTART bit.
• When 1 is written to the TSTOP bit.
[Condition for setting to 1]
• When 1 is written to the TSTART bit.
Symbol
TSTART Timer RB2 count start bit
Symbol
TSTOP Timer RB2 count forced stop bit
TCSTF
Bit
Timer RB2 Control Register (TRBCR)
—
—
—
—
—
Preliminary document
Specifications in this document are tentative and subject to change.
b7
—
0
(1)
Nothing is assigned. The write value must be 0. The read value is 0.
Timer RB2 count status flag
b6
—
0
Bit Name
b5
—
0
(1, 2, 3)
b4
—
0
(4)
[When the TMOD1 bit in the TRBMR register is 0]
0: Count stops
1: Count starts
[When the TMOD1 bit in the TRBMR register is 1]
0: Count stops
1: Count enabled
[When the TMOD1 bit in the TRBMR register is 0]
0: Count stops
1: Count in progress
[When the TMOD1 bit in the TRBMR register is 1]
0: Count stops
1: Count enabled
When 1 is written to this bit, the count is forcibly
stopped. The read value is 0.
b3
—
0
TSTOP
b2
0
TCSTF
Function
b1
0
TSTART
b0
0
Page 244 of 725
16. Timer RB2
R/W
R/W
R/W
—
R