r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 109

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
8.3
Figure 8.2
8.3.1
Count
start
0%
8.3.1.1
Processed as
illegal write
The period for accepting a refresh operation to the watchdog timer (a write to the WDTR register) can be
selected by bits WDTRCS0 and WDTRCS1 in the OFS2 register. Figure 8.2 shows the Watchdog Timer
Refresh Acceptance Period.
When the period from the start of counting to underflow is 100%, a refresh operation executed during the
acceptance period is accepted as shown below. A refresh operation executed during a period other than the
acceptance period is processed as an illegal write, generating a watchdog timer interrupt or watchdog timer
reset (selected by the RIS bit in the RISR register).
Do not perform a refresh operation when the watchdog timer is stopped.
Processed as illegal write
Operations
Items Common to Multiple Modes
(1)
Processed as illegal write
Preliminary document
Specifications in this document are tentative and subject to change.
Refresh Acceptance Period
Watchdog Timer Refresh Acceptance Period
25%
WDTRCS0, WDTRCS1: Bits in OFS2 register
Note:
1. A watchdog timer interrupt or watchdog timer interrupt reset is generated.
Watchdog timer period
Refresh acceptable
(1)
50%
Refresh acceptable
(1)
Refresh acceptable
75%
acceptable
Refresh
Underflow
100%
Refresh acceptance period
100% (WDTRCS1 and WDTRCS0 = 11b)
75% (WDTRCS1 and WDTRCS0 = 10b)
50% (WDTRCS1 and WDTRCS0 = 01b)
25% (WDTRCS1 and WDTRCS0 = 00b)
8. Watchdog Timer
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