r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 477

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
20.4.3
20.4.2.3
20.4.3.1
20.4.3.2
20.4.3.3
In clock synchronous serial I/O mode, the shift clock is generated by activating the transmitter. Set the UART2-
associated registers for transmit operation even if the MCU is used for receive operation only. Dummy data is
output from the TXD2 pin while receiving.
When an internal clock is selected, the shift clock is generated by setting the TE bit in the U2C1 register to 1
(transmission enabled) and placing dummy data in the U2TB register. When an external clock is selected, set
the TE bit to 1 (transmission enabled), place dummy data in the U2TB register, and input an external clock to
the CLK2 pin to generate the shift clock.
If data is received consecutively, an overrun error occurs when the RE bit in the U2C1 register is set to 1 (data
present in the U2RB register) and the next receive data is received in the UART2 receive register. Then, the
OER bit in the U2RB register is set to 1 (overrun error). At this time, the U2RB register retains the previous
receive data. If an overrun error occurs, use a program on the transmitting and receiving sides to resend the data
that caused the error.
To receive data consecutively, set dummy data in the low-order byte in the U2TB register per each receive
operation.
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit is set to 0, or while the external clock is held low when the CKPOL bit is set to 1.
• The RE bit in the U2C1 register = 1 (reception enabled)
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
If an internal clock is selected, set the RE bit in the U2C1 register to 1 after setting the TE bit in the U2C1
register to 1 but before setting dummy data to the U2TB register.
Set the U2RRM bit in the U2C1 register to 1 before reading the last data in continuous receive mode during
master operation.
In I
20.3.3.1 Detection of Start and Stop Conditions.
Not compatible with the CBUS receiver.
10-bit address mode is not supported.
Also cannot be used in a multimaster environment where master transmission/reception of differing data
lengths is performed with the same slave.
The duty cycle of the SCL transmitted by UART2 is 50%. Therefore, when set to high-speed mode (400 kbps),
the low-level width of SCL is 1.25 us. This value does not meet the I
Therefore, the maximum transfer rate in high-speed mode is approximately 380 kbps.
2
C mode, the f1 clock must be oscillating. The f1 frequency input must satisfy the operation described in
Special Mode 1 (I
Preliminary document
Specifications in this document are tentative and subject to change.
Reception
Operating Clock
Supported Modes
Maximum Operating Frequency
2
C Mode)
2
C standard (tLOW = Min 1.3 us).
20. Serial Interface (UART2)
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