r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 313

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
17.2.6
Table 17.5
Notes:
IMFA
IMFB
IMFC
IMFD
OVF
After Reset
Symbol
Bit
b0
b1
b2
b3
b4
b5
b6
b7
1. The edge is selected by bits IOi0 to IOi1 (i = A to D) in registers TRCIO0 and TRCIOR1. However, all of bits
2. PWM mode is selected when bits PWMB, PWMC, and PWMD in the TRCMR register are set to 1.
Address 00145h (TRCSR_0)
Symbol
IOA2 and IOB2 in the TRCIOR0 register and bits IOC2 and IOD2 in the TRCIOR1 register must be set to 1
(input capture function).
Symbol
Bit
IMFC
IMFD
IMFA
IMFB
OVF
Timer RC Status Register (TRCSR)
—
—
—
When the value in the TRCCNT register
is transferred to the TRCGRA register
at the input edge
When the value in the TRCCNT register
is transferred to the TRCGRB register
at the input edge
When the value in the TRCCNT register
is transferred to the TRCGRC register
at the input edge
When the value in the TRCCNT register
is transferred to the TRCGRD register
at the input edge
When the TRCCNT register overflows from FFFFh to 0000h.
Preliminary document
Specifications in this document are tentative and subject to change.
Conditions for Setting Each Flag to 1
OVF
b7
0
Input capture/compare match A flag
Input capture/compare match B flag
Input capture/compare match C flag
Input capture/compare match D flag
Nothing is assigned. The write value must be 1. The read value is 1.
Timer overflow flag
Input Capture Function
b6
—
1
(1)
(1)
(1)
(1)
of the TRCIOA pin.
of the TRCIOB pin.
of the TRCIOC pin.
of the TRCIOD pin.
Bit Name
Timer Mode
b5
—
1
b4
—
1
When the values in registers TRCCNT and TRCGRA match.
When the values in registers TRCCNT and TRCGRB match.
When the values in registers TRCCNT and TRCGRC match.
When the values in registers TRCCNT and TRCGRD match.
Output Compare
[Conditions for setting to 0]
• When 0 is written to this bit after reading it as 1.
• Set to 0 by the DTC acknowledge when the DTC
[Condition for setting to 1]
• Refer to Table 17.5 Conditions for Setting
[Condition for setting to 0]
• When 0 is written to this bit after reading it as 1.
[Condition for setting to 1]
• Refer to Table 17.5 Conditions for Setting
IMFD
Function
is activated by an IMFi interrupt (i = A to D).
Each Flag to 1 .
Each Flag to 1 .
b3
0
IMFC
b2
0
PWM Mode
Function
IMFB
b1
0
IMFA
b0
0
PWM2 Mode
Page 282 of 725
17. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
—
(2)