r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 657

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 26.2
CMDRST Bit (Erase/write sequence reset bit)
CMDERIE Bit (Erase/write error interrupt enable bit)
When the MCU enters stop mode or wait mode while CPU rewrite mode is disabled, the FMR0 register does
not need to be set because the power for the flash memory is automatically turned off and is turned back on
when the MCU exits stop mode or wait mode.
When the FMSTP bit is set to 1 (including during the busy status (the period while the FST7 bit is 0)
immediately after the FMSTP bit is changed from 1 to 0), do not set to low-current-consumption read mode at
the same time.
This bit is used to initialize the flash memory sequence and forcibly stop a program or block erase command.
The program ROM area can be read when resetting the sequence of programming/erasing the data flash area.
If the program or block erase command is forcibly stopped using the CMDRST bit in the FMR0 register,
execute the clear status register command after the FST7 bit in the FST register is set back to 1 (ready). To
program the same address again, execute the block erase command again and ensure it has been completed
normally before programming. If the addresses and blocks where the program or block erase command is
forcibly stopped are allocated in the program area, set the FMR13 bit in the FMR1 register to 1 (lock bit
disabled) before executing the block erase command again.
When the CMDRST bit is set to 1 (erasure/writing stops) during erase-suspend, the suspend status is also
initialized. Thus, execute block erasure again to the block which the block erasure is being suspended.
This bit enables a flash command error interrupt to be generated if the following errors occur:
• Program error
• Block erase error
• Command sequence error
• Block blank check error
If the CMDERIE bit is set to 1 (erase/write error interrupt enabled), an interrupt is generated if the above errors
occur.
If a flash command error interrupt is generated, execute the clear status register command during interrupt
handling.
To change the CMDERIE bit from 0 (erase/write error interrupt disabled) to 1 (erase/write error interrupt
enabled), make the setting as follows:
(1) Execute the clear status register command.
(2) Set the CMDERIE bit to 1.
FMSTP bit
FST7 bit
Preliminary document
Specifications in this document are tentative and subject to change.
Transition to Low-Current-Consumption Read Mode
Do not set to low-current-consumption read mode
0 (busy)
Low-current-consumption read
mode enabled
1 (ready)
26. Flash Memory
Page 626 of 725