r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 159

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
11.1.2
11.1.3
11.1.2.1
11.1.2.2
11.1.2.3
11.1.2.4
11.1.3.1
11.1.3.2
11.1.3.3
11.1.3.4
11.1.3.5
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
An unidentified instruction interrupt is generated when the UND instruction is executed.
An overflow interrupt is generated when the O flag is 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that change the O flag are as follows:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB.
A BRK interrupt is generated when the BRK instruction is executed.
An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers the
INT instruction can specify are 0 to 63. The number is assigned to each peripheral function interrupt. When the
INT instruction is executed specifying the number, the peripheral function interrupt with the same number can
be executed.
For software interrupt numbers 0 to 31, the U flag in the FLG register is saved on the stack during instruction
execution, and the U flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is
restored from the stack when the MCU returns from the interrupt routine. For software interrupt numbers 32 to
63, the U flag does not change state during instruction execution, and the selected SP is used.
Special interrupts are non-maskable.
This interrupt is generated by the watchdog timer.
For details on the watchdog timer, refer to 8. Watchdog Timer.
This interrupt is generated by the oscillation stop detection function.
For details on the oscillation stop detection function, refer to 9. Clock Generation Circuit.
This interrupt is generated by the voltage detection circuit. A non-maskable or maskable interrupt can be
selected by IRQ1SEL bit in the CMPA register.
For details on the voltage detection circuit, refer to 7. Voltage Detection Circuit.
This interrupt is generated by the voltage detection circuit. A non-maskable or maskable interrupt can be
selected by IRQ2SEL bit in the CMPA register.
For details on the voltage detection circuit, refer to 7. Voltage Detection Circuit.
Do not use these interrupts. They are provided exclusively for use in development tools.
Software Interrupts
Special Interrupts
Preliminary document
Specifications in this document are tentative and subject to change.
Undefined Instruction Interrupt
Overflow Interrupt
BRK Interrupt
INT Instruction Interrupt
Watchdog Timer Interrupt
Oscillation Stop Detection Interrupt
Voltage Monitor 1 Interrupt
Voltage Monitor 2 Interrupt
Single-Step Interrupt, Address Break Interrupt
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11. Interrupts