r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 124

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
9.2.10
Table 9.4
i = 0 to 6, 8, j = 0 to 7
XCSEL Bit (XCIN/XCOUT pin connect bit)
IOINSEL Bit (I/O port input function select bit)
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 002B9h
The XCSEL bit is used to select whether to assign XCIN and XCOUT to P4_3 and P4_4. If set to 0, XCIN is
not assigned to P4_3 and XCOUT is not assigned to P4_4. If set to 1, XCIN is assigned to P4_3 and XCOUT is
assigned to P4_4. Refer to 9. Clock Generation Circuit for information on how to set XCIN and XCOUT.
When the PDi_j bit in the PDi register is 1 (output mode), the IOINSEL bit is used to select whether the value
read from the PORTi register is the port latch or the pin input level of the I/O port. If set to 0, the value of the
port latch is read. If set to 1, the pin input level of the I/O port is read.
Table 9.4 lists I/O Port Values Read by Using IOINSEL Bit. The IOINSEL bit can be used to change the input
function of all I/O ports.
Symbol
PDi_j Bit in PDi Register
I/O port values read
IOINSEL I/O port input function
Symbol
XCSEL
Bit
I/O Function Pin Select Register (PINSR)
IOINSEL bit
—
—
—
—
—
—
Preliminary document
Specifications in this document are tentative and subject to change.
I/O Port Values Read by Using IOINSEL Bit
b7
—
0
connect bit
Reserved
select bit
Nothing is assigned. The write value must be 0. The read value is 0.
XCIN/XCOUT pin
Bit Name
b6
—
0
b5
—
0
0
0: XCIN not connected to P4_3, XCOUT not connected to P4_4
1: XCIN connected to P4_3, XCOUT connected to P4_4
Set to 0.
0: The I/O port input function depends on the PDi (i = 0 to 6, 8)
1: The I/O port input function can read the pin input level
0 (Input Mode)
Pin input level
register.
When the PDi_j (j = 0 to 7) bit in the PDi register is set to 0
(input mode), the pin input level can be read.
When the PDi_j bit in the PDi register is set to 1 (output
mode), the value of the port latch can be read.
regardless of the PDi register
b4
—
0
IOINSEL
b3
0
1
b2
—
0
Function
Port latch value
b1
—
0
0
1 (Output Mode)
9. Clock Generation Circuit
XCSEL
b0
0
Pin input level
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1
R/W
R/W
R/W
R/W
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