r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 148

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 10.3
FMR0 Register
FMSTP Bit
operates)
memory
memory
stops)
(flash
(flash
Figure 10.3 shows the Time from Wait Mode after WAIT Instruction Execution to Interrupt Routine Execution.
To use a peripheral function interrupt to exit wait mode, the following items must be set before executing the
WAIT instruction:
(1) Set the interrupt priority level in bits ILVL0 to ILVL2 in the interrupt priority level registers for the
(2) Set the I flag in the FLG register to 1.
(3) Operate the peripheral functions to be used to exit wait mode.
When a peripheral function interrupt is used for return, the time (number of cycles) from interrupt request
generation to the next instruction execution is as shown in Figure 10.3, depending on the settings of the FMSTP
bit in the FMR0 register and the SVC0 bit in the SVDC register.
The CPU clock when a peripheral function interrupt is used to exit wait mode is the clock set by bits CM35,
CM36, and CM37 in the CM3 register. At this time, the CM06 bit in the CM0 register and bits CM16 and
CM17 in the CM1 register are automatically changed.
0
1
Wait mode
peripheral function interrupts that are used to exit wait mode. Also, set 000b (interrupt disabled) in bits
ILVL2 to ILVL0 for the peripheral function interrupts that are not to be used to exit wait mode.
consumption mode disabled)
consumption mode disabled)
consumption mode enabled)
consumption mode enabled)
(transition to low-power
(transition to low-power
(transition to low-power
(transition to low-power
Preliminary document
Specifications in this document are tentative and subject to change.
Time from Wait Mode after WAIT Instruction Execution to Interrupt Routine Execution
SVDC Register
SVC0 Bit
Interrupt request generated
0
1
0
1
stabilization time
Internal power
100 s (max.)
T0
100 s (max.)
100 s (max.)
Internal Power
Stabilization
Time (T0)
0 s
0s
activation sequence
Flash memory
 1 cycle + 60 s (max.)
Period of system clock
Period of system clock
Activation (T1)
Flash Memory
T1
Time until
 1 cycle
restart sequence
Period of CPU clock
Same as above
CPU clock
Supply (T2)
CPU Clock
 2 cycles
Time until
T2
Period of CPU clock
Same as above
Sequence (T3)
Interrupt sequence
 20 cycles
Interrupt
Time for
T3
10. Power Control
The total on the
left amounts to
the time from
wait mode to
interrupt routine
execution.
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Remarks