r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 427

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Table 20.3
Note:
Clock
asynchronous
serial I/O mode
(UART mode)
Special mode 1
(I
Multiprocessor
communication
mode
2
C mode)
1. If an overrun error occurs, the receive data in the U2RB register will not be updated (the previous data will be
read).
Preliminary document
Specifications in this document are tentative and subject to change.
UART2 Specifications (3)
Selectable functions • LSB first/MSB first selection
Pins used
Noise filter
Transfer data format Transfer data length: 8 bits
Transfer clock
Transmit start
conditions
Receive start
conditions
Interrupt request
generation timing
Error detection
Selectable functions • Arbitration lost
Pins used
Transfer data format • Character bits (transfer data): 7 or 8 bits selectable
Selectable function
Specifications other than the above are identical to clock asynchronous serial I/O mode
specifications.
Item
• Serial data logic switching
• TXD and RXD I/O polarity switching
• RXD2 digital filter selection
• SCL2: Transfer clock (master: output, slave: input)
• SDA2: Transfer data (transmit: output, receive: input)
100 ns noise filter for CLK2 and RXD2 input
• Master mode
• Slave mode
To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB
To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB
Start/stop condition detection, no acknowledgement detection, or
acknowledgement detection
• Overrun error
• SDA2 digital delay
• Clock phase setting
• TXD2: Transmit data (output)
• RXD2: Receive data (input)
• CLK2: UART2 operating clock (input when external clock is selected)
• Multiprocessor bits: 1 bit
• Start bits: 1 bit
• Parity bit: No
• Stop bits: 1 or 2 bits selectable
• RXD2 digital filter selection
Whether transmitting or receiving data begins with bit 0 or begins with bit
7 can be selected.
This function inverts the logic of the transmit/receive data. The start and
stop bits are not inverted.
This function inverts the polarities of the TXD pin output and RXD pin
input. The logic levels of all I/O data are inverted.
The RXD2 input signal can be enabled or disabled.
The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n + 1))
fj = f1, f8, f32, or fC1
n = Value set in the U2BRG register (00h to FFh)
The CKDIR bit is set to 1 (external clock): Input from the SCL2 pin
register).
register).
The timing for updating the ABT bit in the U2RB register can be selected.
No digital delay or a delay of 2 to 8 cycles of the U2BRG count source
clock can be selected.
With or without clock delay can be selected.
The RXD2 input signal can be enabled or disabled.
This error occurs if the next data reception starts before the U2RB
register is read and the 7th bit of the next data is received.
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Specification
20. Serial Interface (UART2)
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