r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 525

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.4.2.3
In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal. Figures 21.19 and 21.20 show the Operation Timing in Master Transmit Mode (I
Interface Mode).
The transmit procedure and operation in master transmit mode are shown below:
(1) Set the STOP bit in the SISR register to 0 for initialization. Set the ICE bit in the SICR1 register to 1
(2) After confirming that the bus is released by reading the BBSY bit in the SICR2 register, set bits TRS and
(3) After confirming that the TDRE bit in the SISR register is 1, write transmit data to the SITDR register
(4) When 1 byte of data transmission is completed while the TDRE bit is 1, the TEND bit in the SISR register
(5) When the number of bytes to be transmitted is written to the SITDR register, wait until the TEND bit is set
(6) When the STOP bit in the SISR register is set to 1, return to slave receive mode.
(transfer operation enabled). Then, set bits CPOS_WAIT and MLS in the SIMR1 register and bits CKS0 to
CKS3 in the SICR1 register (initial setting).
MST in the SICR1 register to master transmit mode. Then, write 1 to the BBSY bit and 0 to the SCP bit
with the MOV instruction (start condition generated). This will generate a start condition.
(data in which a slave address and R/W are indicated in the 1st byte). The TDRE bit is automatically set to
0 at this time and data is transferred from registers SITDR to SISDR, and then the TDRE bit is set to 1
again.
is set to 1 at the rising edge of the 9th clock cycle of the transmit clock. After confirming that the slave
device is selected by reading the ACKBR bit in the SIER register, write the 2nd byte of data to the SITDR
register. Write the transmit data after the 2nd byte to the SITDR register every time the TRDE bit is set to
1. Since the slave device is not acknowledged when the ACKBR bit is 1, generate a stop condition or a
repeat start condition. A stop condition is generated by writing 0 to the BBSY bit and 0 to the SCP bit with
the MOV instruction. A repeat start condition is generated by writing 1 to the BBSY bit and 0 to the SCP
bit with the MOV instruction. Clear TEND and NACKF after a repeat start condition has been generated.
The SCL signal is held low until data is ready or a stop condition or a repeat start condition is generated.
to 1 while the TDRE bit is 1. Or wait for NACK (NACKF bit in SISR register = 1) from the receive device
while the ACKE bit in the SIER register is 1 (when the receive acknowledge bit is 1, transfer is halted).
Then, generate a stop condition and set the TEND bit or the NACKF bit to 0.
Preliminary document
Specifications in this document are tentative and subject to change.
Master Transmit Operation
21. Clock Synchronous Serial Interface
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C bus