r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 426

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Table 20.2
Notes:
Clock
asynchronous
serial I/O mode
(UART mode)
1. If an overrun error occurs, the receive data in the U2RB register will not be updated (the previous data will be
2. The framing error flag and the parity error flag are set to 1 when data is transferred from the UART2 receive
read).
register to the U2RB register.
Preliminary document
Specifications in this document are tentative and subject to change.
UART2 Specifications (2)
Pins used
Noise filter
Transfer data format
Transfer clock
Transmit/receive control CTS function, RTS function, or CTS/RTS function disabled selectable
Transmit start conditions To start transmission, the following requirements must be met:
Receive start conditions To start reception, the following requirements must be met:
Interrupt request
generation timing
Error detection
Item
• TXD2: Transmit data (output)
• RXD2: Receive data (input)
• CTS2: Transmit request signal (input)
• RTS2: Receive request signal (output)
• CLK2: Count source clock (input when external clock is selected)
10 ns noise filter for CLK2 and RXD2 input
• Character bits (transfer data): 7, 8, or 9 bits selectable
• Start bits: 1 bit
• Parity bit: Odd, even, or none selectable
• Stop bits: 1 or 2 bits selectable
• The CKDIR bit in the U2MR register is set to 0 (internal clock):
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB
• If the CTS function is selected, input to the CTS2 pin is low.
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• Start bit detection
For transmission, one of the following conditions can be selected.
For reception
• Overrun error
• Framing error
• Parity error
• Error sum flag
fj/(16(n + 1))
fj = f1, f8, f32, or fC1
n = Value set in the U2BRG register: 00h to FFh
fEXT: Input from CLK2 pin
n = Value set in the U2BRG register (00h to FFh)
register).
This error occurs if the next data reception starts before the U2RB
register is read and the bit prior to the last stop bit in the next data is
received.
This error occurs when the set number of stop bits is not detected.
This error occurs if parity is enabled and the number of 1’s in the parity
and character bits does not match the set number of 1’s.
This flag is set to 1 if an overrun, framing, or parity error occurs.
-The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
-The U2IRS bit in the U2C1 register is set to 1 (transmission
When data is transferred from the UART2 receive register to the U2RB
register (at completion of reception).
When data is transferred from the U2TB register to the UART2
transmit register (at start of transmission).
completed):
When data transmission from the UART2 transmit register is
completed.
(2)
(1)
(2)
Specification
20. Serial Interface (UART2)
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