r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 338

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
17.4
Figure 17.19
17.4.1
through digital filter
Input after passing
TRCTRG input
Figure 17.19 shows the Digital Filter Circuit Block Diagram. The TRCIOA to TRCIOD and TRCTRG input
can be latched internally through the digital filter circuit. This circuit consists of three cascaded latch circuits
and a match detection circuit. When the TRCIOA to TRCIOD and TRCTRG input are sampled on the clock
selected by bits DFCK0 and DFCK1 in the TRCDF register and three outputs from the latch circuits match, the
level is passed forward to the next circuit. If they do not match, the previous level is retained. That is, the pulse
input with a width of three sampling clocks or more is recognized as a signal. If not, the change in the signal is
recognized as noise and cancelled.
Do not use the digital filter immediately after a reset. Wait for four cycles of the sampling clock and make the
setting for input capture before using the input capture function.
Sampling clock
TRCTRG input
TRCIOD or
TRCIOA to
Selectable Functions
TRCIOD or
TRCIOA to
fHOCO-F
CKS0 to CKS2 or DFCK0 and DFCK1
TRCCLK
Input Digital Filter for Input Capture
fHOCO
f32
Clock period selected by
Digital Filter Circuit Block Diagram
Preliminary document
Specifications in this document are tentative and subject to change.
f8
f4
f2
f1
CKS0 to CKS2
Timer RC operating clock
CKS0 to CKS2: Bits in TRCCR1 register
IOA0 and IOA1: Bits in TRCIOR0 register
IOD0 and IOD1: Bits in TRCIOR1 register
DFA to DFD, DFTRG, DFCK0, DFCK1: Bits in TRCDF register
D
D
Latch
Latch
C
C
f1 or fHOCO
Q
Q
Sampling clock
f32
D
f8
f1
it is recognized as noise and not transmitted.
Latch
DFCK0 and DFCK1
C
If the output does not match three
Q
successive times,
D
Latch
C
Q
D
Latch
C
Q
Signal transmission is
detection
delayed up to five
sampling clocks.
Match
circuit
DFA to DFD
selection
DFTRG
circuit
IOD0 and IOD1
IOA0 and IOA1
detection
Page 307 of 725
circuit
Edge
17. Timer RC