r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 183

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
11.8
Table 11.13
Timer RC
Timer RE2
Synchronous serial
communication unit
Flash memory
The timer RC, timer RE2, synchronous serial communication unit, and flash memory interrupts each have multiple
interrupt request sources. An interrupt request is generated by the logical OR of several interrupt request sources
and is reflected in the IR bit in the corresponding interrupt control register. Therefore, each of these peripheral
functions has its own interrupt request source status register (status register) and interrupt request source enable
register (enable register) to control the generation of interrupt requests (change of the IR bit in the interrupt control
register). Table 11.13 lists the Registers Associated with Timer RC, Timer RE2, Synchronous Serial
Communication Unit, and Flash Memory Interrupts.
As with other maskable interrupts, the timer RC, timer RE2, synchronous serial communication unit, and flash
memory interrupts are controlled by the combination of the IR bit, bits ILVL0 to ILVL2, and IPL. However, since
each interrupt source is generated by a combination of multiple interrupt request sources, the following differences
from other maskable interrupts apply:
• When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt
• When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR bit
• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set
• When multiple bits in the enable register are set to 1, use the status register to determine which request source
Refer to the chapters of the individual peripheral functions (17. Timer RC, 18. Timer RE2, 21. Clock
Synchronous Serial Interface, and 26. Flash Memory) for the status register and enable register.
For the interrupt control register, refer to 11.4 Interrupt Control.
enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested).
is set to 0 (no interrupt requested).
That is, even if the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
retained.
Also, if 0 is written to the IR bit, this bit is temporarily set to 0 (for five cycles of the CPU clock) and then set back
to 1.
The IR bit is also not automatically set to 0 when the interrupt is acknowledged.
Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to
set individual bits in the status register to 0.
to 1, the IR bit remains 1.
causes an interrupt.
Peripheral Function
Timer RC Interrupt, Timer RE2 Interrupt, Synchronous Serial
Communication Unit Interrupt, and Flash Memory Interrupt (Interrupts with
Multiple Interrupt Request Sources)
Name
Preliminary document
Specifications in this document are tentative and subject to change.
Registers Associated with Timer RC, Timer RE2, Synchronous Serial Communication
Unit, and Flash Memory Interrupts
TRCSR
TREIFR
SISR_0
SISR_1
SISR_2
RDYSTI
BSYAEI
Interrupt Request Source
Status Register of
TRCIER
TREIER
SIER_0
SIER_1
SIER_2
RDYSTIE
BSYAEIE
CMDERIE
Interrupt Request Source
Enable Register of
TRCIC
TRE2IC
SSUIC_0/IICIC_0
SSUIC_1/IICIC_1
SSUIC_2/IICIC_2
FMRDYIC
Interrupt Control
Register
Page 152 of 725
11. Interrupts