r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 728

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
29.7
(1) Timer RB2 stops counting after a reset. Start the count after setting the values in the timer and prescaler.
(2) In the 16-bit timer, when reading registers TRBPRE and TRBPR, access them in 16-bit units.
(3) In programmable one-shot and programmable wait one-shot generation modes, when the TOSSP bit in the
(4) After 1 (count starts) is written to the TSTART bit while the count is stopped, the TCSTF bit in the TRBCR
(5) When the TSTART bit is 0 (count stops), wait for at least two cycles of the CPU clock and then set the
(6) When the TSTART bit is 1 (count starts) or the TCSTF bit is 1 (count in progress), do not change the values of
(7) If 1 (count is forcibly stopped) is written to the TSTOP bit in the TRBCR register during operation, timer RB2
(8) If 1 (one-shot starts) is written to the TOSST bit in the TRBOCR register or 1 (one-shot stops) is written to the
(9) When the underflow signal from timer RJ is used as the count source for timer RB2, set timer RJ to timer
(10) Make sure the TCSTF bit is 1 (count in progress) before writing 1 (one-shot count starts) to the TOSST bit in
(11) In programmable waveform and programmable wait one-shot generation modes of timer RB2, write to the
(12) Insert NOP instructions between writing to and reading from registers TRBPRE and TRBPR while the counter
Note:
TRBOCR register is set to 1 (one-shot stops) and the count is stopped, the timer reloads the value of the reload
register and stops. The count value must be read in the timer before the timer stops. When the TSTART bit in
the TRBCR register is set to 0 (count stops) and the count is stopped, the timer stops and the value of the
reload register is not reloaded.
register remains 0 (count stops) for two or three cycles of the count source. Do not access the registers
associated with timer RB2
is started at the first active edge of the counter source after the TCSTF bit is set to 1.
After 0 (count stops) is written to the TSTART bit during count operation, the TCSTF bit remains 1 for two or
three cycles of the count source. When the TCSTF bit is set to 0, the count is stopped. Do not access the
registers associated with timer RB2
TSTART bit to 1 (count starts) to change the values of registers TRBPRE, TRBPR, and TRBSC.
registers TRBIOC and TRBMR, and the TRBIE bit in the TRBIR register.
stops without any wait time.
TOSSP bit, the TOSSTF bit changes after two to three cycles of the count source. If 1 is written to the TOSSP
bit during the period after 1 is written to the TOSST bit but before the TOSSTF bit can become 1 (one-shot is
operating (including wait period)), depending on the internal state the TOSSTF bit may become 0 (one-shot is
stopped) or 1. Similarly, if 1 is written to the TOSST bit during the period after 1 is written to the TOSSP bit
but before the TOSSTF bit can become 0, the TOSSTF bit may become 0 or 1.
mode, pulse output mode, or event counter mode.
the TRBOCR register. When the TCSTF bit is 0 (count stops), writing 1 (one-shot count starts) to the TOSST
bit has no effect.
TRBSC register before writing to the TRBPR register. The value of the TRBPR register is reflected to the
counter during the underflow of the secondary period after the TRBPR register is written. If registers TRBSC
and TRBPR are written multiple times during the period after the TRBPR register was written but before the
secondary period underflow, the data that was written last will be reflected in the counter. However, do not
write to the TRBSC register only on its own. Write to both the TRBSC and TRBPR registers.
is stopped.
Notes on Timer RB2
1. Registers associated with timer RB2:
TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBPR, and TRBSC
Preliminary document
Specifications in this document are tentative and subject to change.
(1)
other than the TCSTF bit until this bit is set to 1 (count in progress). The count
(1)
other than the TCSTF bit until this bit is set to 0.
29. Usage Notes
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