r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 497

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.2.9
Notes:
21.2.9.1
After Reset
1. Writing 1 to bits CE_ADZ, ORER_AL, RDRF, TEND, and TDRE has no effect. To set any of these bits to 0, write
2. When starting a serial communication while the MS bit in the SIMR2 register is 1 (4-wire bus communication
3. Indicates an overrun error has occurred during reception and reception is terminated in error. If the next serial
4. The RDRF bit is set to 0 when data is read from the SIRDR register. Do not clear this bit by writing 0 when not in
5. Bits TEND and TDRE are set to 0 when data is written to the SITDR register.
6. When the SSU function is used, the TDRE bit is set to 1 when the TE_NAKIE bit in the SIER register is set to 1
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 000EAh (SISR_0)
In the SISR register, the bit functions differ depending on the SSU function and the I
0 after reading it as 1.
mode) and the MST bit in the SICR1 register is 1 (master mode), the CE_ADZ bit is set to 1 if the SCS pin input
is low. Refer to 21.3.3.4 SCS Pin Control and Arbitration .
When the SCS pin input changes from low to high during transfer while the MS bit in the SIMR2 register is 1 (4-
wire bus communication mode) and the MST bit in the SICR1 register is 0 (slave mode), the CE_ADZ bit is set to
1.
data receive operation is completed while the RDRF bit is 1 (data present in the SIRDR register), the ORER_AL
bit is set to 1.
After the ORER_AL bit is set to 1 (overrun error), no reception can be performed while the RDRF bit is 1. Also, no
transmission can be performed while the MST bit is 1 (master mode).
I
(transmission enabled).
Symbol
2
C bus interface mode or when not clearing the RDRF bit after DTC access.
ORER_AL Overrun error flag
CE_ADZ Conflict error flag
Bit
Symbol
NACKF
STOP
RDRF
TEND
TDRE
SI Status Register (SISR)
AAS
Preliminary document
Specifications in this document are tentative and subject to change.
SSU Function
TDRE
b7
0
Reserved
Reserved
Receive data register full flag
Transmit end flag
Transmit data empty flag
TEND
b6
0
Bit Name
(1)
(1, 5)
RDRF
(1)
b5
0
(1, 5, 6)
NACKF
(1, 4)
b4
0
0: No conflict error
1: Conflict error
Set to 0.
0: No overrun error
1: Overrun error
Set to 0.
0: No data in the SIRDR register
1: Data present in the SIRDR register
0: The TDRE bit is 0 when the last bit of transmit
1: The TDRE bit is 1 when the last bit of transmit
0: Data is not transferred from registers SITDR to
1: Data is transferred from registers SITDR to
STOP
data is transmitted
data is transmitted
SISDR
SISDR
b3
0
ORER_AL
b2
0
(2)
21. Clock Synchronous Serial Interface
(3)
Function
AAS
b1
0
2
C bus function.
CE_ADZ
b0
0
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