r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 454

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
20.3.3
Table 20.9
U2TB
U2RB
U2BRG
U2MR
U2C0
U2C1
U2SMR
U2SMR2 IICM2
Register
I
Registers and Settings Used in I
Transfer to U2RB Register and Interrupt Timing.
As shown in Table 20.11, I
IICM bit in the U2SMR register to 1. Because SDA2 transmit output has a delay circuit attached, SDA2 output
does not change state until SCL2 goes low and stabilizes.
2
C mode is provided for use as a simplified I
Special Mode 1 (I
b0 to b7
b0 to b7
b8
ABT
OER
b0 to b7
SMD2 to SMD0 Set to 010b.
CKDIR
CLK0, CLK1
CRS
TXEPT
CRD
NCH
UFORM
TE
TI
RE
RI
U2IRS
IICM
ABC
BBS
CSC
SWC
ALS
STAC
SWC2
SDHI
Preliminary document
Specifications in this document are tentative and subject to change.
Registers and Settings Used in I
Bit
Set transmit data.
Receive data can be read.
ACK or NACK is set in this bit.
Arbitration lost detection flag
Overrun error flag
Set the bit rate.
Set to 0.
Select the count source for the U2BRG
register.
Disabled
Transmit register empty flag
Set to 1.
Set to 1.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Reception complete flag
Set to 1.
Set to 1.
Set the timing for detecting an arbitration
lost.
Bus busy flag
Refer to Table 20.11 I
Set to 1 to enable clock synchronization.
Set to 1 to hold SCL2 output low at the
falling edge of the 9th bit of clock.
Set to 1 to stop SDA2 output when an
arbitration lost is detected.
Set to 0.
Set to 1 to forcibly pull SCL2 low.
Set to 1 to disable SDA2 output.
2
C mode is entered by setting bits SMD2 to SMD0 in the U2MR register and the
2
2
C Mode)
C Mode, Table 20.11 lists the I
Master
2
C Mode Functions . Refer to Table 20.11 I
2
C interface compatible mode. Tables 20.9 and 20.10 list the
2
C Mode (1)
Function
2
C Mode Functions, and Figure 20.14 shows the
Set transmit data.
Receive data can be read.
Disabled
Overrun error flag
Disabled
Set to 010b.
Set to 1.
Select the count source for the U2BRG
register.
Disabled
Transmit register empty flag
Set to 1.
Set to 1.
Set to 1.
Transmit buffer empty flag
Set to 1 to enable reception.
Reception complete flag
Set to 1.
Set to 1.
Disabled
Bus busy flag
Set to 0.
Set to 1 to hold SCL2 output low at the
falling edge of the 9th bit of clock.
Set to 0.
Set to 1 to initialize UART2 when a start
condition is detected.
Set to 1 to forcibly pull SCL2 output low.
Set to 1 to disable SDA2 output.
ACK or NACK is set in this bit.
Set to 1 to enable transmission.
20. Serial Interface (UART2)
Slave
2
C Mode Functions .
Page 423 of 725