r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 529

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.22
21.4.2.4.1
21.4.2.4.2
To generate a repeat start condition after transmitting NACK, use the following procedure:
(1) The same applies as the flow for generating a stop condition until step (5) in 24.4.2.4.
(2) After the RDRF bit in the SISR register is set to 1 at the rising edge of the 9 clock of the receive clock,
(3) Read the SIRDR register after setting to master mode
(4) Write the data indicating a slave address and R/W to the SITDR register.
Note:
The following shows the operation and software flow when a stop condition is detected during I
receive operation.
(1) Detect a stop condition and enter slave receive mode.
(2) Confirm that the BBSY bit in the SICR2 register is 0.
(3) Clear the STOP bit in the SISR register to 0.
(4) Reset the control block.
(master output)
(master output)
SIRDR register
SISDR register
SICR1 register
(slave output)
1. After a repeat start condition is generated (by writing 1 to the BBSY bit and 0 to the SCP bit with the
SISR register
generate a repeat start condition (write 1 to the BBSY bit and 0 to the SCP bit in the SICR2 register with
the MOV instruction).
0 (next receive operation continues).
RCVD bit in
RDRF bit in
processing
MOV instruction), the SCL and SDA signals are held low after 2.5 cycles or later. Be sure to set to
master transmit mode before that.
Program
SDA
SDA
SCL
Preliminary document
Specifications in this document are tentative and subject to change.
Operation Timing in Master Receive Mode (I
Flow for Generating Repeat Start Condition during I
Receive Mode
Operation when Stop Condition is Detected during I2C Master
Receive Operation
Data n - 1
A
9
(5) Read SIRDR register after
Data n - 1
setting RCVD bit to 1.
b7
1
b6
2
b5
3
(6) Generate a stop condition.
b4
4
b3
5
(1)
b2
6
. Then, set the RCVD bit in the SICR1 register to
2
C bus Interface Mode) (2)
b1
7
(7) Set RCVD bit to 0 after reading
SIRDR register.
21. Clock Synchronous Serial Interface
Data n
b0
8
A/A
Data n
9
(8) Set to slave receive mode.
2
C Master
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2
C master