r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 556

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 22.5
22.4.2
Figure 22.5 shows an Operation Example during Header Field Reception in slave mode. Figures 22.6 to 22.8
show Examples of Header Field Reception Flowchart.
During header field reception, the hardware LIN operates as follows:
(1) When 1 (timer RJ input enabled, RXD input disabled) is written to the LSTART bit in the LINCT register
(2) If a low level is input for a duration equal to or longer than the period set in timer RJ, the hardware LIN
(3) The hardware LIN receives a Synch Field (55h) and measures the period of the start bit and bits 0 to 6
(4) When Synch Field measurement is completed, the SFDCT flag in the LINST register is set to 1. If the
(5) After Synch Field measurement is completed, a transfer rate is calculated from the timer RJ count value.
(6) After the hardware LIN completes receiving the ID field, it performs communication for a response field.
LINCT register
TRJIC register
LINST register
LINST register
RXDSF bit in
SBDCT bit in
SFDCT bit in
of the hardware LIN, Synch Break detection is enabled.
detects it as a Synch Break. At this time, the SBDCT bit in the LINST register is set to 1 (Synch Break is
detected or Synch Break generation is completed). If the SBIE bit in the LINCT register is set to 1 (Synch
Break detection interrupt enabled), a timer RJ interrupt is generated. Then the hardware LIN enters Synch
Field measurement.
using timer RJ. At this time, whether or not to input the Synch Field signal to RXD of UART0 can be
selected by the SBE bit in the LINCT register.
SFIE bit in the LINCT register is set to 1, a timer RJ interrupt is generated.
The rate is set in UART0 and the TRJ register of timer RJ is set again. Then the hardware LIN receives an
ID field via UART0.
for UART0
RXD input
Slave Mode
RXD pin
IR bit in
Preliminary document
Specifications in this document are tentative and subject to change.
Operation Example during Header Field Reception
The above diagram applies under the following condition:
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
(1)
1 is written to
LSTART bit in
LINCT register
Synch Break
Set to 0 by acknowledgment of an interrupt request
(2)
(3)
This period is measured
1 is written to
B1CLR bit in
LINST register
or by a program
Synch Field
(4)
(5)
The flag is set to 0 after
Synch Field measurement
is completed.
1 is written to B0CLR
bit in LINST register
IDENTIFIER
22. Hardware LIN
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