r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 505

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.6
21.3.2
21.3.2.1
Figure 21.6 shows the Initialization in Clock Synchronous Communication Mode. Before data transmission or
reception, set the TE_NAKIE bit in the SIER register to 0 (transmission disabled) and the RE_ STIE bit to 0
(reception disabled) for initialization.
To change the communication mode (select clock synchronous communication mode by the mode select MS bit
in the SIMR2 register) or the communication format, set the TE_NAKIE bit to 0 and the RE_STIE bit to 0
before making the change.
Even if the RE_STIE bit is set to 0, the contents of bits RDRF and ORER_AL in the SISR register and the
SIRDR register are retained.
Note:
Clock Synchronous Communication Mode
SIER register
SIMR1 register
SIMR2 register
SICR1 register
SIER register
1. To set the ORER_AL bit to 0, write 0 after reading it as 1.
SSBR register Set bits BS0 to BS3
Preliminary document
Specifications in this document are tentative and subject to change.
Initialization in Clock Synchronous Communication Mode
Initialization in Clock Synchronous Communication Mode
SISR register ORER_AL bit  0
SICR1 register Set MST bit
SIMR2 register MS bit  0
RE_STIE bit  0
TE_NAKIE bit  0
CPHS bit  0
CPOS_WAIT bit  0
Set MLS bit
SCKS bit  1
Set SOOS bit
Set bits CKS0 to CKS2
Set RCVD bit
RE_STIE bit  1 (receive)
TE_NAKIE bit  1 (transmit)
Set bits RIE, TEIE, and TIE
Start
End
(1)
Reception disabled
Transmission disabled
SSU data transfer length setting
Mode selected (clock synchronous communication mode)
Clock phase selected (data change at odd edge)
Clock state selected (high when clock stops)
MSB/LSB first selected
Master/slave mode selected
SSCK pin selected (serial clock pin)
SSCK pin open-drain output selected
Clock period setting
Receive disable bit setting
Overrun error flag cleared
Transmission/reception enable setting
Interrupt enable setting
21. Clock Synchronous Serial Interface
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