r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 527

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.4.2.3.1
21.4.2.3.2
21.4.2.4
To generate a repeat start condition after receiving NACK, use the following procedure:
(1) Confirm a NACK error.
(2) Generate a repeat start condition (write 1 to the BBSY bit and 1 to the SCP bit in the SICR2 register with
(3) Confirm the rising edge of the SCL signal.
(4) Clear bits TEND and NACKF in the SISR register.
The following shows the operation and software flow when a start condition/stop condition is detected during
I
(1) Detect an arbitration lost and enter slave receive mode.
(2) Clear bits TDRE and ORER_AL in the SISR register.
(3) Confirm the BBSY bit in the SICR2 register.
When 1: Enter slave address reception.
When 0: Either of the host/slave can operate.
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal. Figures 21.21 and 21.22 show the Operation Timing in Master Receive Mode
(I
The receive procedure and operation in master receive mode are as follows:
(1) After setting the TEND bit in the SISR register to 0, set the TRS bit in the SICR1 register to 0 to switch
(2) Reception is started by performing a dummy read of the SIRDR register. The receive clock is output in
(3) When one frame of data reception is completed, the RDRF bit in the SISR register is set to 1 at the rising
(4) Reception can be performed continuously by reading the SIRDR register every time the RDRF bit is set to
(5) If the next frame is the last receive frame, set the RCVD bit in the SICR1 register to 1 (next receive
(6) When the RDRF bit is set to 1 at the rising edge of the 9th clock cycle of the receive clock, generate a stop
(7) When the STOP bit in the SISR register is set to 1, read the SIRDR register. Then, set the RCVD bit to 0
(8) Return to slave receive mode.
2
2
C master transmit operation.
C bus Interface Mode).
the MOV instruction)
from master transmit mode to master receive mode. Then, set the TDRE bit in the SISR register to 0.
synchronization with the internal clock and data is received. The master device outputs the level set by the
CEIE_ACKBT bit in the SIER register to the SDA pin at the rising edge of the 9th clock cycle of the
receive clock.
edge of the 9th clock cycle of the receive clock. If the SIRDR register is read at this time, the received data
can be read and the RDRF bit is set to 0 at the same time.
1. If reading of the SIRDR register is delayed by another process and the 8th clock cycle falls while the
RDRF bit is 1, the SCL signal is held low until the SIRDR register is read. No stop condition or repeat start
condition can be generated at this time.
operation disabled) and the CEIE_ACKBT bit to 1 before reading the SIRDR register. This enables
returning NACK to the slave device and a stop condition can be generated after the next reception.
condition.
(next receive operation continues).
Preliminary document
Specifications in this document are tentative and subject to change.
Master Receive Operation
Flow for Generating Repeat Start Condition during I
Transmit Mode
Operation when Start Condition/Stop Condition is Detected during
I
2
C Master Transmit Operation
21. Clock Synchronous Serial Interface
2
C Master
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