r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 433

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
20.2.4
Notes:
After Reset
1. If bits CLK0 and CLK1 are changed, set the U2BRG register again.
2. Do not select 11b (fC1) while in I
3. Can only be selected in SIO/UART mode. In other modes, because the CRD bit is set to 1 (CTS/RTS function
4. Can only be set in SIO/UART mode. In other modes, set to 1 (CTS/RTS function disabled).
5. Set to 1 (pins TXD2/SDA2 and SCL2 are set to N-channel open-drain output) while in I
6. When UART2 is not used, set the NCH bit to 0 (pins TXD2/SDA2 and SCL2 are set to CMOS output).
7. Can only be set in SIO mode. In other modes, set to 0 (transmit data is output at the falling edge and receive data
8. Can only be selected while data transfer length is 8 bits in SIO/UART mode. In I
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 000C4h
disabled), the value set to this bit is invalid.
is input at the rising edge of the transfer clock).
modes other than I
Symbol UFORM
UFORM Transfer format select bit
Symbol
CKPOL CLK polarity select bit
TXEPT
Bit
CLK0
CLK1
CRD
CRS
NCH
UART2 Transmit/Receive Control Register 0 (U2C0)
Preliminary document
Specifications in this document are tentative and subject to change.
b7
0
U2BRG count source select bits
CTS/RTS function select bit
Transmit register empty flag
CTS/RTS disable bit
Data output select bit
2
C and SIO/UART mode, set to 0 (LSB first).
CKPOL
b6
0
Bit Name
2
NCH
C mode.
b5
0
(4)
(7, 6)
(7)
(8)
(3)
CRD
b4
0
(1)
TXEPT
Enabled when CRD = 0
0: CTS function selected
1: RTS function selected
0: Data present in the transmit register
1: No data in the transmit register
0: CTS/RTS function enabled
1: CTS/RTS function disabled
0: Pins TXD2/SDA2 and SCL2 are set to CMOS
1: Pins TXD2/SDA2 and SCL2 are set to N-
0: Transmit data is output at the falling edge and
1: Transmit data is output at the rising edge and
0: LSB first
1: MSB first
b1 b0
0 0: f1
0 1: f8
1 0: f32
1 1: fC1
b3
(transmission in progress)
(transmission completed)
output
channel open-drain output
receive data is input at the rising edge of the
transfer clock
receive data is input at the falling edge of the
transfer clock
1
(2)
CRS
b2
0
Function
CLK1
b1
0
2
C mode, set to 1 (MSB first). In
20. Serial Interface (UART2)
CLK0
2
C mode.
b0
0
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R/W
R/W
R/W
R/W
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