r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 543

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Table 21.12
1 Tcyc = 1/f1 (s)
21.4.7
IICTCHALF
When CKS3 to CKS0 = 1000b, the bit synchronization circuit does not function even if the high-level width of
the SCL signal is 600 ns or less (breach of the I
■ Common to the SSU/I
• To read the receive buffer in master mode using the DTC, set the number of transfers minus 1 in the DTC
• After the number of transfers minus 1 of receive data is transferred, an RXI interrupt is generated. Set the
• If clearing of the RDRF bit is delayed and the last byte is transferred, the SCL signal is held low and a hang-up
• Setting of the RCVD bit in the SICR1 register must be performed during the receive operation of the last byte.
■ SSU Function
• After the last data is received, an RXI interrupt is generated. Set the RE_STIE bit in the SIER register to 0
■ I
• After the last data is received, an RXI interrupt is generated. Confirm that the SCLO bit (SCL monitor flag) in
• When the STOP bit in the SISR register is set to 1 (a stop condition is detected after the frame is transferred),
transfer count register.
RCVD bit in the SICR1 register to 1 (next receive operation disabled) and then set the RDRF bit in the SISR
register to 0 (no data in the SIRDR register).
occurs when the I
(reception disabled) and the RCVD bit 0 (next receive operation continues) before reading the SIRDR register
by software.
the SICR2 register is set to 0 before generating a stop condition.
read the SIRDR register. Then set the RCVD bit 0 (next receive operation continues).
2
0
0
1
C bus Function
Coordination with DTC
Preliminary document
Specifications in this document are tentative and subject to change.
Time between Changing SCL Signal from Low Output to High Impedance and
Monitoring SCL Signal
IICTCTW1
2
C bus function is used. When the SSU function is used, an overrun error occurs.
0
1
0
2
SICR1 Register
C bus functions
CKS3
0
1
0
1
0
1
2
C specification) (When the operating clock is set to 20 MHz).
CKS2
0
1
0
1
0
1
0
1
0
1
0
1
21. Clock Synchronous Serial Interface
SCL Monitoring Time (MT)
19.5 Tcyc
17.5 Tcyc
41.5 Tcyc
19.5 Tcyc
17.5 Tcyc
41.5 Tcyc
37.5 Tcyc
85.5 Tcyc
7.5 Tcyc
2.5 Tcyc
8.5 Tcyc
7.5 Tcyc
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