r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 490

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Notes:
21.2.5.2
After Reset
1. In master mode, make the setting according to the required transfer rate. For details on the transfer rate, refer to
2. Rewrite the TRS bit between transfer frames.
3. In slave receive mode, when the first 7 bits after the start condition match the slave address set in the SIMR2
4. If arbitration is lost in master mode of I
5. In multimaster operation, use the MOV instruction to set bits TRS and MST.
6. When the TRS bit is 1, do not set the RCVD bit to 1.
7. When an overrun error occurs in master receive mode of clock synchronous serial mode, the MST bit is set to 0
8. When the MST bit is 0 (slave mode), do not set the RCVD bit to 1.
9. When 0 is written to the ICE bit or 1 is written to the SIRST bit in the SICR2 register while the I
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 000E6h (SICR1_0)
Tables 21.9 and 21.10 Transfer Rate Examples . In slave mode, a transfer clock is used for maintaining the data
setup time in transmit mode. For details on this function, refer to 21.4.2.5.1 Maintaining Data Setup Time
during I
register and the 8th bit is 1, the TRS bit is set to 1 (transmit mode).
mode is entered.
and slave receive mode is entered.
operating, the values of the BBSY bit in the SICR2 register and the STOP bit in the SISR register may be
undefined. Refer to 21.5 Notes on Clock Synchronous Serial Interface .
Symbol
Symbol
RCVD
Bit
CKS0
CKS1
CKS2
CKS3
MST
TRS
ICE
2
C Slave Transmit Operation .
Preliminary document
Specifications in this document are tentative and subject to change.
I
2
ICE
b7
C bus Function
0
Transfer clock select bits
Transmit/receive select bit
(2, 3, 4, 5, 6)
Master/slave select bit
Receive disable bit
I
2
C bus interface enable bit
RCVD
b6
0
Bit Name
MST
b5
(8)
0
(4, 5, 7)
2
(1)
C bus interface mode, bits MST and TRS are set to 0 and slave receive
(9)
TRS
b4
0
0: Receive mode
1: Transmit mode
0: Slave mode
1: Master mode
After the SIRDR register is read while TRS = 0,
0: Next receive operation continues
1: Next receive operation disabled
0: Output from SCL and SDA is disabled
1: Transfer with I
b3 b2 b1 b0
0 0 0 0: f1/28
0 0 0 1: f1/40
0 0 1 0: f1/48
0 0 1 1: f1/64
0 1 0 0: f1/80
0 1 0 1: f1/100
0 1 1 0: f1/112
0 1 1 1: f1/128
1 0 0 0: f1/56
1 0 0 1: f1/80
1 0 1 0: f1/96
1 0 1 1: f1/128
1 1 0 0: f1/160
1 1 0 1: f1/200
1 1 1 0: f1/224
1 1 1 1: f1/256
CKS3
(Input to SCL and SDA is enabled)
b3
0
CKS2
b2
0
2
C bus function is enabled
21. Clock Synchronous Serial Interface
Function
CKS1
b1
0
CKS0
b0
0
2
C bus function is
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