r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 83

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 6.6
6.3.4
The voltage monitor 0 reset is due to the on-chip voltage detection 0 circuit. The voltage detection 0 circuit
monitors the voltage applied to the VCC pin. Vdet0 is the detection level. To use the voltage monitoring 0 reset,
set the LVDAS bit in the OFS register to 0 (voltage monitoring 0 reset enabled after reset). The Vdet0 detection
level can be changed by setting bits VDSEL0 and VDSEL1 in the OFS register.
When the input voltage to the VCC pin falls to the Vdet0 level or lower, the CPU, SFRs and I/O ports are
initialized.
When the voltage applied to the VCC pin next rises to the Vdet0 level or higher, the low-speed on-chip
oscillator clock count starts. When the low-speed on-chip oscillator clock count reaches 32, the internal reset
signal goes high and the MCU proceeds to the reset sequence (refer to Figure 6.2). The low-speed on-chip
oscillator clock with no division is automatically selected as the CPU clock after a reset.
To use the power-on reset, set the LVDAS bit and enable the voltage monitor 0 reset.
Bits VDSEL0, VDSEL1, and LVDAS cannot be changed by a program. To set these bits, write values to b4 to
b6 at address 0FFFFh using a flash programmer.
For details on the OFS register, refer to 6.2.4 Option Function Select Register (OFS).
For details on the states of the SFRs after a voltage monitor 0 reset, refer to 3.2 Special Function Registers
(SFRs).
The internal RAM is not initialized. If the voltage applied to the VCC pin falls to Vdet0 or lower while writing
to the internal RAM, the RAM values will be undefined.
For details on the voltage monitor 0 reset, refer to 7. Voltage Detection Circuit.
Figure 6.6 shows the Voltage Monitor 0 Reset Circuit Example and Operation.
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. For details, refer to the
2. To use the power-on reset, set the LVDAS bit in the OFS register to 0 and enable the voltage monitor 0
Voltage Monitor 0 Reset
Voltage Detection Circuit chapter.
reset.
Preliminary document
Specifications in this document are tentative and subject to change.
Voltage Monitor 0 Reset Circuit Example and Operation
External power VCC
Internal reset signal
V
0.5V
det0
circuit response time
Voltage detection 0
fLOCO
1
 32
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6. Resets