r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 373

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
18.2.16 Timer RE2 Interrupt Flag Register (TREIFR)
TRECR register
RTCRST bit in
CMIF Bit (Compare match interrupt flag)
OVIF Bit (Overflow interrupt flag)
After reset by
Bit
b0
b1
b2
b3
b4
b5
b6
b7
After Reset
[Conditions for setting to 0]
• When 0 is written to this bit after reading it. If the result of reading this bit is 1, writing 0 to this bit will set it
• When an interrupt from the DTC is automatically cleared.
[Condition for setting to 1]
• The contents of registers TRESEC and TREMIN match.
[Conditions for setting to 0]
• When 0 is written to this bit after reading it. If the result of reading this bit is 1, writing 0 to this bit will set it
• When an interrupt from the DTC is automatically cleared.
[Condition for setting to 1]
• The 8-bit counter overflows.
to 0.
If the result of reading this bit is 0, writing 0 to this bit will not change its value. If this bit changes from 0 to 1
after the read, the bit will remain 1 even if 0 is written. Writing 1 has no effect.
to 0.
If the result of reading this bit is 0, writing 0 to this bit will not change its value. If this bit changes from 0 to 1
after the read, the bit will remain 1 even if 0 is written. Writing 1 has no effect.
Address 0017Ah
Symbol TADJSF
RSTADJ
ADJ30S
TADJSF Disabled in compare match timer mode.
Symbol
CMIF
OVIF
ALIE
in Compare Match Timer Mode
—
—
Bit
Preliminary document
Specifications in this document are tentative and subject to change.
Compare match interrupt flag
Overflow interrupt flag
Set to 0.
Nothing is assigned. The write value must be 0. The read value is 0.
b7
0
0
b6
—
0
0
Bit Name
b5
—
0
0
RSTADJ ADJ30S
b4
0
0
0: No interrupt requested
1: Interrupt requested
b3
0
0
ALIE
b2
0
0
Function
OVIF
b1
0
0
CMIF
b0
0
0
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18. Timer RE2
R/W
R/W
R/W
R/W
W
W
—
R