r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 523

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Table 21.11
RE_STIE, TE_NAKIE, RIE, TEIE, TIE: Bits in SIER register
ORER_AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in SISR register
Transmit data empty
Transmit end
Receive data full
Stop condition detection
NACK detection
Arbitration lost
Overrun error
21.4.1.3
The I
synchronous serial mode. Table 21.11 lists the Interrupt Requests of I
Because these interrupt requests are assigned to the I
must be determined using bits.
When generation conditions listed in Table 21.11 are met, an I
Set the interrupt generation conditions to 0 by the I
Note that bits TDRE and TEND in the SIER register are automatically set to 0 by writing transmit data to the
SITDR register and the RDRF bit is automatically set to 0 by reading the SIRDR register. In particular, the
TDRE bit is set to 0 when transmit data is written to the SITDR register and set to 1 when data is transferred
from registers SITDR to SISDR. If the TDRE bit is further set to 0, an additional 1 byte may be transmitted.
Because the data is retained in the transmit buffer, the data is shifted to the shift register by a trigger (the TDRE
bit in the SISR register is 0), and thus the same data is retransmitted.
Also, set the RE_STIE bit in the SIER register to 1 (stop condition detection interrupt request enabled) only
when the STOP bit in the SISR register is 0.
Interrupt Request
2
C bus interface has six interrupt requests in I
Preliminary document
Specifications in this document are tentative and subject to change.
Interrupt Requests
Interrupt Requests of I
NAKI TE_NAKIE = 1 and ORER_AL = 1
STPI RE_STIE = 1 and STOP = 1
RXI
TXI
TEI
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
(or TE_NAKIE = 1 and NACKF = 1)
2
C bus Interface
Generation Condition
2
C bus interface interrupt routine.
2
C bus interface mode and four interrupt requests in clock
2
C bus interface interrupt vector table, interrupt sources
2
C bus interface interrupt request is generated.
2
C bus Interface.
21. Clock Synchronous Serial Interface
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
I
2
C bus
Format
Clock synchronous
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Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
serial