r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 436

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
20.2.7
Note:
20.2.8
Notes:
After Reset
After Reset
1. When the RXD2 digital filter is enabled, noise that is three or fewer pulses of the baud rate clock is reduced. For
1. When the MP bit is set to 1 (multiprocessor communication enabled), the settings of bits PRY and PRYE in the
2. Enabled only when transfer data length is 7 bits or 8 bits in UART mode. Set to 0 in other modes.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 000D0h
Address 000C8h
details, refer to 20.3.2.7 RXD2 Digital Filter Select Function.
Can only be set in UART mode and multiprocessor communication mode. In other modes, set to 0 (RXD2 digital
filter disabled).
U2MR register are disabled.
Write to the U2SMR5 register using the MOV instruction.
Symbol
Symbol
Symbol
Symbol
DF2EN
Bit
Bit
MPIE
UART2 Digital Filter Function Select Register (U2RXDF)
UART2 Special Mode Register 5 (U2SMR5)
MP
—
—
—
—
—
—
—
—
—
—
—
—
—
Preliminary document
Specifications in this document are tentative and subject to change.
b7
b7
—
—
0
0
Nothing is assigned. The write value must be 0. The read value is 0.
RXD2 digital filter enable bit
Nothing is assigned. The write value must be 0. The read value is 0.
Multiprocessor communication
enable bit
Nothing is assigned. The write value must be 0. The read value is 0.
Multiprocessor communication
control bit
Nothing is assigned. The write value must be 0. The read value is 0.
Reserved
b6
b6
—
—
0
0
(1, 2)
Bit Name
Bit Name
b5
b5
—
—
0
0
MPIE
b4
b4
—
0
0
Set to 0.
0: Multiprocessor communication disabled
1: Multiprocessor communication enabled
This bit is enabled when the MP bit is set to 1
(multiprocessor communication enabled).
When the MPIE bit is set to 1, the following will result:
• Receive data in which the multiprocessor bit is 0 is
• On receiving receive data in which the
ignored. Setting of the RI bit in the U2C1 register and
bits OER and FER in the U2RB register to 1 is
disabled.
multiprocessor bit is 1, the MPIE bit is set to 0 and a
receive operation other than multiprocessor
communication is performed.
When the MPIE bit is 0, operation is the same as
normal receive operation.
0: RXD2 digital filter disabled
1: RXD2 digital filter enabled
b3
b3
—
—
0
0
DF2EN
b2
b2
—
0
0
Function
Function
b1
b1
—
—
0
0
20. Serial Interface (UART2)
MP
b0
—
b0
0
0
Page 405 of 725
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—